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hw/sd: Fix sun4i allwinner-sdhost for U-Boot

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Trying to run U-Boot for Cubieboard (Allwinner A10) fails because it cannot
access SD card. The problem is that FIFO register in current
allwinner-sdhost implementation is at the address corresponding to
Allwinner H3, but not A10.
Linux kernel is not affected since Linux driver uses DMA access and does
not use FIFO register for reading/writing.

This patch adds new class parameter `is_sun4i` and based on that
parameter uses register at offset 0x100 either as FIFO register (if
sun4i) or as threshold register (if not sun4i; in this case register at
0x200 is FIFO register).

Tested with U-Boot and Linux kernel image built for Cubieboard and
OrangePi PC.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221112214900.24152-1-strahinja.p.jankovic@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Strahinja Jankovic 2022-11-21 11:45:12 +00:00 committed by Peter Maydell
parent a082fab9d2
commit 93e2da36ed
2 changed files with 47 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
hw/sd/allwinner-sdhost.c
View File

@ -65,7 +65,7 @@ enum {
REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
REG_SD_THLDC = 0x100, /* Card Threshold Control */
REG_SD_THLDC = 0x100, /* Card Threshold Control / FIFO (sun4i only)*/
REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
@ -415,10 +415,29 @@ static void allwinner_sdhost_dma(AwSdHostState *s)
}
}
static uint32_t allwinner_sdhost_fifo_read(AwSdHostState *s)
{
uint32_t res = 0;
if (sdbus_data_ready(&s->sdbus)) {
sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
le32_to_cpus(&res);
allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
allwinner_sdhost_auto_stop(s);
allwinner_sdhost_update_irq(s);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
__func__);
}
return res;
}
static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
unsigned size)
{
AwSdHostState *s = AW_SDHOST(opaque);
AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
uint32_t res = 0;
switch (offset) {
@ -508,8 +527,12 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
res = s->dmac_irq;
break;
case REG_SD_THLDC: /* Card Threshold Control */
res = s->card_threshold;
case REG_SD_THLDC: /* Card Threshold Control or FIFO register (sun4i) */
if (sc->is_sun4i) {
res = allwinner_sdhost_fifo_read(s);
} else {
res = s->card_threshold;
}
break;
case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
res = s->startbit_detect;
@ -531,16 +554,7 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
res = s->status_crc;
break;
case REG_SD_FIFO: /* Read/Write FIFO */
if (sdbus_data_ready(&s->sdbus)) {
sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
le32_to_cpus(&res);
allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
allwinner_sdhost_auto_stop(s);
allwinner_sdhost_update_irq(s);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
__func__);
}
res = allwinner_sdhost_fifo_read(s);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
@ -553,11 +567,20 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
return res;
}
static void allwinner_sdhost_fifo_write(AwSdHostState *s, uint64_t value)
{
uint32_t u32 = cpu_to_le32(value);
sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
allwinner_sdhost_auto_stop(s);
allwinner_sdhost_update_irq(s);
}
static void allwinner_sdhost_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
AwSdHostState *s = AW_SDHOST(opaque);
uint32_t u32;
AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
trace_allwinner_sdhost_write(offset, value, size);
@ -657,18 +680,18 @@ static void allwinner_sdhost_write(void *opaque, hwaddr offset,
s->dmac_irq = value;
allwinner_sdhost_update_irq(s);
break;
case REG_SD_THLDC: /* Card Threshold Control */
s->card_threshold = value;
case REG_SD_THLDC: /* Card Threshold Control or FIFO (sun4i) */
if (sc->is_sun4i) {
allwinner_sdhost_fifo_write(s, value);
} else {
s->card_threshold = value;
}
break;
case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
s->startbit_detect = value;
break;
case REG_SD_FIFO: /* Read/Write FIFO */
u32 = cpu_to_le32(value);
sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
allwinner_sdhost_auto_stop(s);
allwinner_sdhost_update_irq(s);
allwinner_sdhost_fifo_write(s, value);
break;
case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
@ -834,12 +857,14 @@ static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
{
AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
sc->max_desc_size = 8 * KiB;
sc->is_sun4i = true;
}
static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
{
AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
sc->max_desc_size = 64 * KiB;
sc->is_sun4i = false;
}
static const TypeInfo allwinner_sdhost_info = {

1
include/hw/sd/allwinner-sdhost.h
View File

@ -130,6 +130,7 @@ struct AwSdHostClass {
/** Maximum buffer size in bytes per DMA descriptor */
size_t max_desc_size;
bool is_sun4i;
};