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target/mips: Style improvements in mips_malta.c 

Fixes mostly errors and warnings reported by 'checkpatch.pl -f'.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1566216496-17375-16-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic 2019-08-19 14:07:54 +02:00
parent 6c06ea4cec
commit 94818443cf
1 changed files with 128 additions and 88 deletions
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180
hw/mips/mips_malta.c
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@ -117,11 +117,12 @@ static void malta_fpga_update_display(void *opaque)
MaltaFPGAState *s = opaque; MaltaFPGAState *s = opaque;
for (i = 7 ; i >= 0 ; i--) { for (i = 7 ; i >= 0 ; i--) {
if (s->leds & (1 << i)) if (s->leds & (1 << i)) {
leds_text[i] = '#'; leds_text[i] = '#';
else } else {
leds_text[i] = ' '; leds_text[i] = ' ';
} }
}
leds_text[8] = '\0'; leds_text[8] = '\0';
qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
@ -140,8 +141,6 @@ static void malta_fpga_update_display(void *opaque)
* Typical device names include Microchip 24C02SC or SGS Thomson ST24C02. * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
*/ */
//~ #define DEBUG
#if defined(DEBUG) #if defined(DEBUG)
# define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__) # define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
#else #else
@ -156,7 +155,7 @@ struct _eeprom24c0x_t {
uint8_t scl; uint8_t scl;
uint8_t sda; uint8_t sda;
uint8_t data; uint8_t data;
//~ uint16_t size; /* uint16_t size; */
uint8_t contents[256]; uint8_t contents[256];
}; };
@ -164,22 +163,38 @@ typedef struct _eeprom24c0x_t eeprom24c0x_t;
static eeprom24c0x_t spd_eeprom = { static eeprom24c0x_t spd_eeprom = {
.contents = { .contents = {
/* 00000000: */ 0x80,0x08,0xFF,0x0D,0x0A,0xFF,0x40,0x00, /* 00000000: */
/* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01, 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
/* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x00,0x00, /* 00000008: */
/* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0xFF, 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
/* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00, /* 00000010: */
/* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
/* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000018: */
/* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0, 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
/* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000020: */
/* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
/* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000028: */
/* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000030: */
/* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000038: */
/* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
/* 00000040: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000048: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000050: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000058: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000060: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000068: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000070: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 00000078: */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
}, },
}; };
@ -349,7 +364,8 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
/* SWITCH Register */ /* SWITCH Register */
case 0x00200: case 0x00200:
val = 0x00000000; /* All switches closed */ /* ori a3, a3, low(ram_low_size) */
val = 0x00000000;
break; break;
/* STATUS Register */ /* STATUS Register */
@ -388,10 +404,11 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
/* GPINP Register */ /* GPINP Register */
case 0x00a08: case 0x00a08:
/* IN = OUT until a real I2C control is implemented */ /* IN = OUT until a real I2C control is implemented */
if (s->i2csel) if (s->i2csel) {
val = s->i2cout; val = s->i2cout;
else } else {
val = 0x00; val = 0x00;
}
break; break;
/* I2CINP Register */ /* I2CINP Register */
@ -469,8 +486,9 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
/* SOFTRES Register */ /* SOFTRES Register */
case 0x00500: case 0x00500:
if (val == 0x42) if (val == 0x42) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
break; break;
/* BRKRES Register */ /* BRKRES Register */
@ -801,26 +819,27 @@ static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr,
/* jalrc t8 */ /* jalrc t8 */
} }
/* ROM and pseudo bootloader /*
* ROM and pseudo bootloader
The following code implements a very very simple bootloader. It first *
loads the registers a0 to a3 to the values expected by the OS, and * The following code implements a very very simple bootloader. It first
then jump at the kernel address. * loads the registers a0 to a3 to the values expected by the OS, and
* then jump at the kernel address.
The bootloader should pass the locations of the kernel arguments and *
environment variables tables. Those tables contain the 32-bit address * The bootloader should pass the locations of the kernel arguments and
of NULL terminated strings. The environment variables table should be * environment variables tables. Those tables contain the 32-bit address
terminated by a NULL address. * of NULL terminated strings. The environment variables table should be
* terminated by a NULL address.
For a simpler implementation, the number of kernel arguments is fixed *
to two (the name of the kernel and the command line), and the two * For a simpler implementation, the number of kernel arguments is fixed
tables are actually the same one. * to two (the name of the kernel and the command line), and the two
* tables are actually the same one.
The registers a0 to a3 should contain the following values: *
a0 - number of kernel arguments * The registers a0 to a3 should contain the following values:
a1 - 32-bit address of the kernel arguments table * a0 - number of kernel arguments
a2 - 32-bit address of the environment variables table * a1 - 32-bit address of the kernel arguments table
a3 - RAM size in bytes * a2 - 32-bit address of the environment variables table
* a3 - RAM size in bytes
*/ */
static void write_bootloader(uint8_t *base, int64_t run_addr, static void write_bootloader(uint8_t *base, int64_t run_addr,
int64_t kernel_entry) int64_t kernel_entry)
@ -859,14 +878,23 @@ static void write_bootloader(uint8_t *base, int64_t run_addr,
} else { } else {
stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */ stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */
} }
stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */ /* lui sp, high(ENVP_ADDR) */
stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */ stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff));
stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */ /* ori sp, sp, low(ENVP_ADDR) */
stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */ stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff));
stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */ /* lui a1, high(ENVP_ADDR) */
stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16)); /* lui a3, high(ram_low_size) */ stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff)); /* ori a3, a3, low(ram_low_size) */ /* ori a1, a1, low(ENVP_ADDR) */
stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
/* lui a2, high(ENVP_ADDR + 8) */
stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
/* ori a2, a2, low(ENVP_ADDR + 8) */
stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
/* lui a3, high(ram_low_size) */
stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
/* ori a3, a3, low(ram_low_size) */
stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
/* Load BAR registers as done by YAMON */ /* Load BAR registers as done by YAMON */
stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */ stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
@ -976,8 +1004,9 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
va_list ap; va_list ap;
int32_t table_addr; int32_t table_addr;
if (index >= ENVP_NB_ENTRIES) if (index >= ENVP_NB_ENTRIES) {
return; return;
}
if (string == NULL) { if (string == NULL) {
prom_buf[index] = 0; prom_buf[index] = 0;
@ -1043,9 +1072,11 @@ static int64_t load_kernel (void)
if (loaderparams.initrd_filename) { if (loaderparams.initrd_filename) {
initrd_size = get_image_size(loaderparams.initrd_filename); initrd_size = get_image_size(loaderparams.initrd_filename);
if (initrd_size > 0) { if (initrd_size > 0) {
/* The kernel allocates the bootmap memory in the low memory after /*
the initrd. It takes at most 128kiB for 2GB RAM and 4kiB * The kernel allocates the bootmap memory in the low memory after
pages. */ * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
* pages.
*/
initrd_offset = (loaderparams.ram_low_size - initrd_size initrd_offset = (loaderparams.ram_low_size - initrd_size
- (128 * KiB) - (128 * KiB)
- ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK; - ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
@ -1071,9 +1102,10 @@ static int64_t load_kernel (void)
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename); prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
if (initrd_size > 0) { if (initrd_size > 0) {
prom_set(prom_buf, prom_index++, "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s", prom_set(prom_buf, prom_index++,
xlate_to_kseg0(NULL, initrd_offset), initrd_size, "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
loaderparams.kernel_cmdline); xlate_to_kseg0(NULL, initrd_offset),
initrd_size, loaderparams.kernel_cmdline);
} else { } else {
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline); prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
} }
@ -1113,9 +1145,11 @@ static void main_cpu_reset(void *opaque)
cpu_reset(CPU(cpu)); cpu_reset(CPU(cpu));
/* The bootloader does not need to be rewritten as it is located in a /*
read only location. The kernel location and the arguments table * The bootloader does not need to be rewritten as it is located in a
location does not change. */ * read only location. The kernel location and the arguments table
* location does not change.
*/
if (loaderparams.kernel_filename) { if (loaderparams.kernel_filename) {
env->CP0_Status &= ~(1 << CP0St_ERL); env->CP0_Status &= ~(1 << CP0St_ERL);
} }
@ -1213,9 +1247,11 @@ void mips_malta_init(MachineState *machine)
DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA); DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA);
MaltaState *s = MIPS_MALTA(dev); MaltaState *s = MIPS_MALTA(dev);
/* The whole address space decoded by the GT-64120A doesn't generate /*
exception when accessing invalid memory. Create an empty slot to * The whole address space decoded by the GT-64120A doesn't generate
emulate this feature. */ * exception when accessing invalid memory. Create an empty slot to
* emulate this feature.\
*/
empty_slot_init(0, 0x20000000); empty_slot_init(0, 0x20000000);
qdev_init_nofail(dev); qdev_init_nofail(dev);
@ -1331,8 +1367,10 @@ void mips_malta_init(MachineState *machine)
exit(1); exit(1);
} }
} }
/* In little endian mode the 32bit words in the bios are swapped, /*
a neat trick which allows bi-endian firmware. */ * In little endian mode the 32bit words in the bios are swapped,
* a neat trick which allows bi-endian firmware.
*/
#ifndef TARGET_WORDS_BIGENDIAN #ifndef TARGET_WORDS_BIGENDIAN
{ {
uint32_t *end, *addr; uint32_t *end, *addr;
@ -1386,8 +1424,10 @@ void mips_malta_init(MachineState *machine)
piix4_devfn = piix4_init(pci_bus, &isa_bus, 80); piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
/* Interrupt controller */ /*
/* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */ * Interrupt controller
* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
*/
s->i8259 = i8259_init(isa_bus, i8259_irq); s->i8259 = i8259_init(isa_bus, i8259_irq);
isa_bus_irqs(isa_bus, s->i8259); isa_bus_irqs(isa_bus, s->i8259);