target/loongarch: Add fixed point atomic instruction translation
This includes:
- LL.{W/D}, SC.{W/D}
- AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[_DB].{W/D}
- AM{MAX/MIN}[_DB].{WU/DU}
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-9-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Song Gao
Richard Henderson
parent
bb79174d4e
commit
94b02d57b0
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@ -0,0 +1,113 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv t0 = tcg_temp_new();
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tcg_gen_addi_tl(t0, src1, a->imm);
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tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, mop);
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tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr));
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tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval));
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gen_set_gpr(a->rd, dest, EXT_NONE);
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tcg_temp_free(t0);
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return true;
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}
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static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv src2 = gpr_src(ctx, a->rd, EXT_NONE);
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TCGv t0 = tcg_temp_new();
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TCGv val = tcg_temp_new();
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TCGLabel *l1 = gen_new_label();
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TCGLabel *done = gen_new_label();
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tcg_gen_addi_tl(t0, src1, a->imm);
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tcg_gen_brcond_tl(TCG_COND_EQ, t0, cpu_lladdr, l1);
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tcg_gen_movi_tl(dest, 0);
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tcg_gen_br(done);
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gen_set_label(l1);
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tcg_gen_mov_tl(val, src2);
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/* generate cmpxchg */
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tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval,
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val, ctx->mem_idx, mop);
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tcg_gen_setcond_tl(TCG_COND_EQ, dest, t0, cpu_llval);
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gen_set_label(done);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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tcg_temp_free(t0);
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tcg_temp_free(val);
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return true;
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}
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static bool gen_am(DisasContext *ctx, arg_rrr *a,
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void (*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
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MemOp mop)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv val = gpr_src(ctx, a->rk, EXT_NONE);
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if (a->rd != 0 && (a->rj == a->rd || a->rk == a->rd)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Warning: source register overlaps destination register"
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"in atomic insn at pc=0x" TARGET_FMT_lx "\n",
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ctx->base.pc_next - 4);
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return false;
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}
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func(dest, addr, val, ctx->mem_idx, mop);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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return true;
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}
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TRANS(ll_w, gen_ll, MO_TESL)
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TRANS(sc_w, gen_sc, MO_TESL)
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TRANS(ll_d, gen_ll, MO_TEUQ)
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TRANS(sc_d, gen_sc, MO_TEUQ)
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TRANS(amswap_w, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
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TRANS(amswap_d, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
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TRANS(amadd_w, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
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TRANS(amadd_d, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
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TRANS(amand_w, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
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TRANS(amand_d, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
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TRANS(amor_w, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
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TRANS(amor_d, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
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TRANS(amxor_w, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
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TRANS(amxor_d, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
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TRANS(ammax_w, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
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TRANS(ammax_d, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
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TRANS(ammin_w, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
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TRANS(ammin_d, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
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TRANS(ammax_wu, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
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TRANS(ammax_du, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
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TRANS(ammin_wu, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
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TRANS(ammin_du, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
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TRANS(amswap_db_w, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
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TRANS(amswap_db_d, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
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TRANS(amadd_db_w, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
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TRANS(amadd_db_d, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
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TRANS(amand_db_w, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
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TRANS(amand_db_d, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
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TRANS(amor_db_w, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
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TRANS(amor_db_d, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
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TRANS(amxor_db_w, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
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TRANS(amxor_db_d, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
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TRANS(ammax_db_w, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
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TRANS(ammax_db_d, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
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TRANS(ammin_db_w, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
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TRANS(ammin_db_d, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
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TRANS(ammax_db_wu, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
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TRANS(ammax_db_du, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
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TRANS(ammin_db_wu, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
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TRANS(ammin_db_du, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
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@ -172,7 +172,7 @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
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if (a->imm) {
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temp = tcg_temp_new();
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tcg_gen_addi_tl(temp, addr, a->im);
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tcg_gen_addi_tl(temp, addr, a->imm);
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addr = temp;
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}
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@ -193,3 +193,47 @@ stle_b 0011 10000111 11100 ..... ..... ..... @rrr
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stle_h 0011 10000111 11101 ..... ..... ..... @rrr
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stle_w 0011 10000111 11110 ..... ..... ..... @rrr
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stle_d 0011 10000111 11111 ..... ..... ..... @rrr
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#
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# Fixed point atomic instruction
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#
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ll_w 0010 0000 .............. ..... ..... @rr_i14s2
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sc_w 0010 0001 .............. ..... ..... @rr_i14s2
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ll_d 0010 0010 .............. ..... ..... @rr_i14s2
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sc_d 0010 0011 .............. ..... ..... @rr_i14s2
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amswap_w 0011 10000110 00000 ..... ..... ..... @rrr
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amswap_d 0011 10000110 00001 ..... ..... ..... @rrr
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amadd_w 0011 10000110 00010 ..... ..... ..... @rrr
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amadd_d 0011 10000110 00011 ..... ..... ..... @rrr
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amand_w 0011 10000110 00100 ..... ..... ..... @rrr
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amand_d 0011 10000110 00101 ..... ..... ..... @rrr
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amor_w 0011 10000110 00110 ..... ..... ..... @rrr
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amor_d 0011 10000110 00111 ..... ..... ..... @rrr
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amxor_w 0011 10000110 01000 ..... ..... ..... @rrr
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amxor_d 0011 10000110 01001 ..... ..... ..... @rrr
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ammax_w 0011 10000110 01010 ..... ..... ..... @rrr
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ammax_d 0011 10000110 01011 ..... ..... ..... @rrr
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ammin_w 0011 10000110 01100 ..... ..... ..... @rrr
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ammin_d 0011 10000110 01101 ..... ..... ..... @rrr
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ammax_wu 0011 10000110 01110 ..... ..... ..... @rrr
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ammax_du 0011 10000110 01111 ..... ..... ..... @rrr
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ammin_wu 0011 10000110 10000 ..... ..... ..... @rrr
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ammin_du 0011 10000110 10001 ..... ..... ..... @rrr
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amswap_db_w 0011 10000110 10010 ..... ..... ..... @rrr
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amswap_db_d 0011 10000110 10011 ..... ..... ..... @rrr
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amadd_db_w 0011 10000110 10100 ..... ..... ..... @rrr
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amadd_db_d 0011 10000110 10101 ..... ..... ..... @rrr
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amand_db_w 0011 10000110 10110 ..... ..... ..... @rrr
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amand_db_d 0011 10000110 10111 ..... ..... ..... @rrr
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amor_db_w 0011 10000110 11000 ..... ..... ..... @rrr
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amor_db_d 0011 10000110 11001 ..... ..... ..... @rrr
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amxor_db_w 0011 10000110 11010 ..... ..... ..... @rrr
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amxor_db_d 0011 10000110 11011 ..... ..... ..... @rrr
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ammax_db_w 0011 10000110 11100 ..... ..... ..... @rrr
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ammax_db_d 0011 10000110 11101 ..... ..... ..... @rrr
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ammin_db_w 0011 10000110 11110 ..... ..... ..... @rrr
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ammin_db_d 0011 10000110 11111 ..... ..... ..... @rrr
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ammax_db_wu 0011 10000111 00000 ..... ..... ..... @rrr
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ammax_db_du 0011 10000111 00001 ..... ..... ..... @rrr
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ammin_db_wu 0011 10000111 00010 ..... ..... ..... @rrr
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ammin_db_du 0011 10000111 00011 ..... ..... ..... @rrr
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@ -154,6 +154,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
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#include "insn_trans/trans_shift.c.inc"
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#include "insn_trans/trans_bit.c.inc"
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#include "insn_trans/trans_memory.c.inc"
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#include "insn_trans/trans_atomic.c.inc"
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static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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{
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