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ppc patch queue for 2017-03-14 

This set has a handful og bugfixes to go into qemu-2.9.  This includes
 an update to the dtc/libfdt submodule which will fix the build errors
 seen on some distributions.
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170314' into staging

ppc patch queue for 2017-03-14

This set has a handful og bugfixes to go into qemu-2.9.  This includes
an update to the dtc/libfdt submodule which will fix the build errors
seen on some distributions.

# gpg: Signature made Tue 14 Mar 2017 04:00:41 GMT
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.9-20170314:
  dtc: Update submodule to avoid build errors
  pseries: Don't expose PCIe extended config space on older machine types
  target/ppc: fix cpu_ov setting for 32-bit
  target/ppc: Fix wrong number of UAMR register

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2017-03-14 10:13:19 +00:00
parent 4d04351f4c 28df75d8d1
commit 94b5d57d2f
6 changed files with 15 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
dtc

@ -1 +1 @@
Subproject commit fa8bc7f928ac25f23532afc8beb2073efc8fb063
Subproject commit 558cd81bdd432769b59bff01240c44f82cfb1a9d

9
hw/ppc/spapr.c
View File

@ -3163,8 +3163,13 @@ DEFINE_SPAPR_MACHINE(2_9, "2.9", true);
/*
* pseries-2.8
*/
#define SPAPR_COMPAT_2_8 \
HW_COMPAT_2_8
#define SPAPR_COMPAT_2_8 \
HW_COMPAT_2_8 \
{ \
.driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
.property = "pcie-extended-configuration-space", \
.value = "off", \
},
static void spapr_machine_2_8_instance_options(MachineState *machine)
{

4
hw/ppc/spapr_pci.c
View File

@ -1321,7 +1321,7 @@ static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset,
_FDT(fdt_setprop(fdt, offset, "assigned-addresses",
(uint8_t *)rp.assigned, rp.assigned_len));
if (pci_is_express(dev)) {
if (sphb->pcie_ecs && pci_is_express(dev)) {
_FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
}
@ -1858,6 +1858,8 @@ static Property spapr_phb_properties[] = {
DEFINE_PROP_UINT32("numa_node", sPAPRPHBState, numa_node, -1),
DEFINE_PROP_BOOL("pre-2.8-migration", sPAPRPHBState,
pre_2_8_migration, false),
DEFINE_PROP_BOOL("pcie-extended-configuration-space", sPAPRPHBState,
pcie_ecs, true),
DEFINE_PROP_END_OF_LIST(),
};

2
include/hw/pci-host/spapr.h
View File

@ -80,6 +80,8 @@ struct sPAPRPHBState {
uint32_t numa_node;
bool pcie_ecs; /* Allow access to PCIe extended config space? */
/* Fields for migration compatibility hacks */
bool pre_2_8_migration;
uint32_t mig_liobn;

2
target/ppc/cpu.h
View File

@ -1408,7 +1408,7 @@ int ppc_compat_max_threads(PowerPCCPU *cpu);
#define SPR_601_UDECR (0x006)
#define SPR_LR (0x008)
#define SPR_CTR (0x009)
#define SPR_UAMR (0x00C)
#define SPR_UAMR (0x00D)
#define SPR_DSCR (0x011)
#define SPR_DSISR (0x012)
#define SPR_DAR (0x013) /* DAE for PowerPC 601 */

2
target/ppc/translate.c
View File

@ -818,7 +818,7 @@ static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
if (is_isa300(ctx)) {
tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
}
tcg_gen_extract_tl(cpu_ov, cpu_ov, 63, 1);
tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
}
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}