target/riscv: Fix the PMP is locked check when using TOR
The RISC-V spec says: if PMP entry i is locked and pmpicfg.A is set to TOR, writes to pmpaddri-1 are ignored. The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which is incorrect. Update the pmp_is_locked() function to not check the supporting fields and instead enforce the lock functionality in the pmpaddr write operation. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 2831241458163f445a89bd59c59990247265b0c6.1618812899.git.alistair.francis@wdc.com
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@ -59,16 +59,6 @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
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return 0;
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return 0;
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}
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}
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/* In TOR mode, need to check the lock bit of the next pmp
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* (if there is a next)
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*/
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const uint8_t a_field =
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pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg);
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if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) &&
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(PMP_AMATCH_TOR == a_field)) {
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return 1;
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}
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return 0;
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return 0;
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}
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}
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@ -380,7 +370,23 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
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target_ulong val)
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target_ulong val)
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{
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{
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trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
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trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
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if (addr_index < MAX_RISCV_PMPS) {
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if (addr_index < MAX_RISCV_PMPS) {
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/*
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* In TOR mode, need to check the lock bit of the next pmp
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* (if there is a next).
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*/
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if (addr_index + 1 < MAX_RISCV_PMPS) {
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uint8_t pmp_cfg = env->pmp_state.pmp[addr_index + 1].cfg_reg;
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if (pmp_cfg & PMP_LOCK &&
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PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"ignoring pmpaddr write - pmpcfg + 1 locked\n");
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return;
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}
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}
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if (!pmp_is_locked(env, addr_index)) {
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if (!pmp_is_locked(env, addr_index)) {
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env->pmp_state.pmp[addr_index].addr_reg = val;
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env->pmp_state.pmp[addr_index].addr_reg = val;
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pmp_update_rule(env, addr_index);
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pmp_update_rule(env, addr_index);
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