OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

alpha_typhoon: QOM'ify Typhoon PCI host bridge

Browse Source 
Introduce type constant and cast macro. Don't access DeviceState
or PCIHostState indirectly through parent fields.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber 2012-08-20 19:07:57 +02:00 committed by Anthony Liguori
parent 4240abff5a
commit 94dd91d651
1 changed files with 13 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
hw/alpha_typhoon.c
View File

@ -15,6 +15,8 @@
#include "exec-memory.h" #include "exec-memory.h"
#define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost"
typedef struct TyphoonCchip { typedef struct TyphoonCchip {
MemoryRegion region; MemoryRegion region;
uint64_t misc; uint64_t misc;
@ -40,8 +42,12 @@ typedef struct TyphoonPchip {
TyphoonWindow win[4]; TyphoonWindow win[4];
} TyphoonPchip; } TyphoonPchip;
#define TYPHOON_PCI_HOST_BRIDGE(obj) \
OBJECT_CHECK(TyphoonState, (obj), TYPE_TYPHOON_PCI_HOST_BRIDGE)
typedef struct TyphoonState { typedef struct TyphoonState {
PCIHostState host; PCIHostState host;
TyphoonCchip cchip; TyphoonCchip cchip;
TyphoonPchip pchip; TyphoonPchip pchip;
MemoryRegion dchip_region; MemoryRegion dchip_region;
@ -700,16 +706,16 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
MemoryRegion *addr_space = get_system_memory(); MemoryRegion *addr_space = get_system_memory();
MemoryRegion *addr_space_io = get_system_io(); MemoryRegion *addr_space_io = get_system_io();
DeviceState *dev; DeviceState *dev;
PCIHostState *p;
TyphoonState *s; TyphoonState *s;
PCIHostState *phb;
PCIBus *b; PCIBus *b;
int i; int i;
dev = qdev_create(NULL, "typhoon-pcihost"); dev = qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE);
qdev_init_nofail(dev); qdev_init_nofail(dev);
p = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); s = TYPHOON_PCI_HOST_BRIDGE(dev);
s = container_of(p, TyphoonState, host); phb = FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(dev));
/* Remember the CPUs so that we can deliver interrupts to them. */ /* Remember the CPUs so that we can deliver interrupts to them. */
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
@ -763,10 +769,10 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
memory_region_add_subregion(addr_space, 0x801fc000000ULL, memory_region_add_subregion(addr_space, 0x801fc000000ULL,
&s->pchip.reg_io); &s->pchip.reg_io);
b = pci_register_bus(&s->host.busdev.qdev, "pci", b = pci_register_bus(dev, "pci",
typhoon_set_irq, sys_map_irq, s, typhoon_set_irq, sys_map_irq, s,
&s->pchip.reg_mem, addr_space_io, 0, 64); &s->pchip.reg_mem, addr_space_io, 0, 64);
s->host.bus = b; phb->bus = b;
/* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */ /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */
memory_region_init_io(&s->pchip.reg_iack, &alpha_pci_iack_ops, b, memory_region_init_io(&s->pchip.reg_iack, &alpha_pci_iack_ops, b,
@ -818,7 +824,7 @@ static void typhoon_pcihost_class_init(ObjectClass *klass, void *data)
} }
static const TypeInfo typhoon_pcihost_info = { static const TypeInfo typhoon_pcihost_info = {
.name = "typhoon-pcihost", .name = TYPE_TYPHOON_PCI_HOST_BRIDGE,
.parent = TYPE_SYS_BUS_DEVICE, .parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(TyphoonState), .instance_size = sizeof(TyphoonState),
.class_init = typhoon_pcihost_class_init, .class_init = typhoon_pcihost_class_init,