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tcg: Add tcg_gen_vec_shl{shr}{sar}8i_i32

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Implement tcg_gen_vec_shl{shr}{sar}8i_tl by adding corresponging i32 OP.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20210624105023.3852-5-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
LIU Zhiwei 2021-06-24 18:50:22 +08:00 committed by Richard Henderson
parent 04f2a8bbc0
commit 950ee59026
2 changed files with 38 additions and 0 deletions
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10
include/tcg/tcg-op-gvec.h
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@ -408,8 +408,11 @@ void tcg_gen_vec_add16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
void tcg_gen_vec_sub8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
void tcg_gen_vec_sub16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
void tcg_gen_vec_shl8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t);
void tcg_gen_vec_shl16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t);
void tcg_gen_vec_shr8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t);
void tcg_gen_vec_shr16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t);
void tcg_gen_vec_sar8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t);
void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t);
#if TARGET_LONG_BITS == 64
@ -417,14 +420,21 @@ void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t);
#define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i64
#define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i64
#define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i64
#define tcg_gen_vec_shl8i_tl tcg_gen_vec_shl8i_i64
#define tcg_gen_vec_shr8i_tl tcg_gen_vec_shr8i_i64
#define tcg_gen_vec_sar8i_tl tcg_gen_vec_sar8i_i64
#define tcg_gen_vec_shl16i_tl tcg_gen_vec_shl16i_i64
#define tcg_gen_vec_shr16i_tl tcg_gen_vec_shr16i_i64
#define tcg_gen_vec_sar16i_tl tcg_gen_vec_sar16i_i64
#else
#define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i32
#define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i32
#define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i32
#define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i32
#define tcg_gen_vec_shl8i_tl tcg_gen_vec_shl8i_i32
#define tcg_gen_vec_shr8i_tl tcg_gen_vec_shr8i_i32
#define tcg_gen_vec_sar8i_tl tcg_gen_vec_sar8i_i32
#define tcg_gen_vec_shl16i_tl tcg_gen_vec_shl16i_i32
#define tcg_gen_vec_shr16i_tl tcg_gen_vec_shr16i_i32
#define tcg_gen_vec_sar16i_tl tcg_gen_vec_sar16i_i32

28
tcg/tcg-op-gvec.c
View File

@ -2678,6 +2678,13 @@ void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
tcg_gen_andi_i64(d, d, mask);
}
void tcg_gen_vec_shl8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c)
{
uint32_t mask = dup_const(MO_8, 0xff << c);
tcg_gen_shli_i32(d, a, c);
tcg_gen_andi_i32(d, d, mask);
}
void tcg_gen_vec_shl16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c)
{
uint32_t mask = dup_const(MO_16, 0xffff << c);
@ -2736,6 +2743,13 @@ void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
tcg_gen_andi_i64(d, d, mask);
}
void tcg_gen_vec_shr8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c)
{
uint32_t mask = dup_const(MO_8, 0xff >> c);
tcg_gen_shri_i32(d, a, c);
tcg_gen_andi_i32(d, d, mask);
}
void tcg_gen_vec_shr16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c)
{
uint32_t mask = dup_const(MO_16, 0xffff >> c);
@ -2808,6 +2822,20 @@ void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
tcg_temp_free_i64(s);
}
void tcg_gen_vec_sar8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c)
{
uint32_t s_mask = dup_const(MO_8, 0x80 >> c);
uint32_t c_mask = dup_const(MO_8, 0xff >> c);
TCGv_i32 s = tcg_temp_new_i32();
tcg_gen_shri_i32(d, a, c);
tcg_gen_andi_i32(s, d, s_mask); /* isolate (shifted) sign bit */
tcg_gen_muli_i32(s, s, (2 << c) - 2); /* replicate isolated signs */
tcg_gen_andi_i32(d, d, c_mask); /* clear out bits above sign */
tcg_gen_or_i32(d, d, s); /* include sign extension */
tcg_temp_free_i32(s);
}
void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c)
{
uint32_t s_mask = dup_const(MO_16, 0x8000 >> c);