target/ppc: Use gvec to decode XVCPSGN[SD]P
Moved XVCPSGNSP and XVCPSGNDP to decodetree and used gvec to translate them. xvcpsgnsp: rept loop master patch 8 12500 0,00561400 0,00537900 (-4.2%) 25 4000 0,00562100 0,00400000 (-28.8%) 100 1000 0,00696900 0,00416300 (-40.3%) 500 200 0,02211900 0,00840700 (-62.0%) 2500 40 0,09328600 0,02728300 (-70.8%) 8000 12 0,27295300 0,06867800 (-74.8%) xvcpsgndp: rept loop master patch 8 12500 0,00556300 0,00584200 (+5.0%) 25 4000 0,00482700 0,00431700 (-10.6%) 100 1000 0,00585800 0,00464400 (-20.7%) 500 200 0,01565300 0,00839700 (-46.4%) 2500 40 0,05766500 0,02430600 (-57.8%) 8000 12 0,19875300 0,07947100 (-60.0%) Like the previous instructions there seemed to be a improvement on translation time. Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221019125040.48028-10-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Lucas Mateus Castro (alqotel)
Daniel Henrique Barboza
parent
a5b3680519
commit
95a89d3118
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@ -762,6 +762,8 @@ XVNABSDP 111100 ..... 00000 ..... 111101001 .. @XX2
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XVNABSSP 111100 ..... 00000 ..... 110101001 .. @XX2
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XVNEGDP 111100 ..... 00000 ..... 111111001 .. @XX2
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XVNEGSP 111100 ..... 00000 ..... 110111001 .. @XX2
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XVCPSGNDP 111100 ..... ..... ..... 11110000 ... @XX3
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XVCPSGNSP 111100 ..... ..... ..... 11010000 ... @XX3
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## VSX Scalar Multiply-Add Instructions
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@ -729,62 +729,6 @@ VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
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VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP)
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VSX_SCALAR_MOVE_QP(xscpsgnqp, OP_CPSGN, SGN_MASK_DP)
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#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
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static void glue(gen_, name)(DisasContext *ctx) \
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{ \
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TCGv_i64 xbh, xbl, sgm; \
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if (unlikely(!ctx->vsx_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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xbh = tcg_temp_new_i64(); \
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xbl = tcg_temp_new_i64(); \
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sgm = tcg_temp_new_i64(); \
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get_cpu_vsr(xbh, xB(ctx->opcode), true); \
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get_cpu_vsr(xbl, xB(ctx->opcode), false); \
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tcg_gen_movi_i64(sgm, sgn_mask); \
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switch (op) { \
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case OP_ABS: { \
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tcg_gen_andc_i64(xbh, xbh, sgm); \
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tcg_gen_andc_i64(xbl, xbl, sgm); \
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break; \
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} \
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case OP_NABS: { \
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tcg_gen_or_i64(xbh, xbh, sgm); \
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tcg_gen_or_i64(xbl, xbl, sgm); \
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break; \
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} \
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case OP_NEG: { \
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tcg_gen_xor_i64(xbh, xbh, sgm); \
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tcg_gen_xor_i64(xbl, xbl, sgm); \
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break; \
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} \
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case OP_CPSGN: { \
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TCGv_i64 xah = tcg_temp_new_i64(); \
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TCGv_i64 xal = tcg_temp_new_i64(); \
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get_cpu_vsr(xah, xA(ctx->opcode), true); \
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get_cpu_vsr(xal, xA(ctx->opcode), false); \
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tcg_gen_and_i64(xah, xah, sgm); \
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tcg_gen_and_i64(xal, xal, sgm); \
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tcg_gen_andc_i64(xbh, xbh, sgm); \
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tcg_gen_andc_i64(xbl, xbl, sgm); \
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tcg_gen_or_i64(xbh, xbh, xah); \
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tcg_gen_or_i64(xbl, xbl, xal); \
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tcg_temp_free_i64(xah); \
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tcg_temp_free_i64(xal); \
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break; \
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} \
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} \
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set_cpu_vsr(xT(ctx->opcode), xbh, true); \
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set_cpu_vsr(xT(ctx->opcode), xbl, false); \
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tcg_temp_free_i64(xbh); \
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tcg_temp_free_i64(xbl); \
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tcg_temp_free_i64(sgm); \
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}
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VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
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VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
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#define TCG_OP_IMM_i64(FUNC, OP, IMM) \
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static void FUNC(TCGv_i64 t, TCGv_i64 b) \
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{ \
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@ -852,6 +796,59 @@ TRANS(XVABSSP, do_vsx_msb_op, MO_32, do_xvabs_vec, do_xvabssp_i64)
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TRANS(XVNABSSP, do_vsx_msb_op, MO_32, do_xvnabs_vec, do_xvnabssp_i64)
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TRANS(XVNEGSP, do_vsx_msb_op, MO_32, do_xvneg_vec, do_xvnegsp_i64)
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static void do_xvcpsgndp_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b)
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{
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tcg_gen_andi_i64(a, a, SGN_MASK_DP);
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tcg_gen_andi_i64(b, b, ~SGN_MASK_DP);
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tcg_gen_or_i64(t, a, b);
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}
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static void do_xvcpsgnsp_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b)
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{
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tcg_gen_andi_i64(a, a, SGN_MASK_SP);
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tcg_gen_andi_i64(b, b, ~SGN_MASK_SP);
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tcg_gen_or_i64(t, a, b);
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}
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static void do_xvcpsgn_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
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{
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uint64_t msb = (vece == MO_32) ? SGN_MASK_SP : SGN_MASK_DP;
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tcg_gen_bitsel_vec(vece, t, tcg_constant_vec_matching(t, vece, msb), a, b);
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}
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static bool do_xvcpsgn(DisasContext *ctx, arg_XX3 *a, unsigned vece)
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{
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static const TCGOpcode vecop_list[] = {
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0
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};
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static const GVecGen3 op[] = {
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{
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.fni8 = do_xvcpsgnsp_i64,
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.fniv = do_xvcpsgn_vec,
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.opt_opc = vecop_list,
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.vece = MO_32
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},
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{
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.fni8 = do_xvcpsgndp_i64,
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.fniv = do_xvcpsgn_vec,
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.opt_opc = vecop_list,
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.vece = MO_64
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},
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};
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REQUIRE_INSNS_FLAGS2(ctx, VSX);
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REQUIRE_VSX(ctx);
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tcg_gen_gvec_3(vsr_full_offset(a->xt), vsr_full_offset(a->xa),
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vsr_full_offset(a->xb), 16, 16, &op[vece - MO_32]);
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return true;
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}
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TRANS(XVCPSGNSP, do_xvcpsgn, MO_32)
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TRANS(XVCPSGNDP, do_xvcpsgn, MO_64)
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#define VSX_CMP(name, op1, op2, inval, type) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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@ -165,9 +165,6 @@ GEN_XX3FORM(name, opc2, opc3 | 1, fl2)
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GEN_XX2FORM_DCMX(xvtstdcdp, 0x14, 0x1E, PPC2_ISA300),
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GEN_XX2FORM_DCMX(xvtstdcsp, 0x14, 0x1A, PPC2_ISA300),
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GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
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GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
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GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
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GEN_VSX_XFORM_300(xsaddqp, 0x04, 0x00, 0x0),
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GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
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