target/arm: add data cache invalidation cp15 instruction to cortex-r5
The cp15, CRn=15, opc1=0, CRm=5, opc2=0 instruction invalidates all the data cache on the cortex-r5. Implementing it as a NOP. Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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@ -1082,6 +1082,8 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
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.access = PL1_RW, .type = ARM_CP_CONST },
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{ .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST },
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{ .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
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.opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
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REGINFO_SENTINEL
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};
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