tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i
Following the implementation of tcg_gen_gvec_3i, add a four-vector and immediate operand expansion method. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-34-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Matheus Ferst
Cédric Le Goater
parent
41c2877f52
commit
9620ae01b8
@ -218,6 +218,25 @@ typedef struct {
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bool write_aofs;
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bool write_aofs;
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} GVecGen4;
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} GVecGen4;
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typedef struct {
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/*
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* Expand inline as a 64-bit or 32-bit integer. Only one of these will be
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* non-NULL.
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*/
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void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64, int64_t);
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void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32, int32_t);
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/* Expand inline with a host vector type. */
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void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec, int64_t);
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/* Expand out-of-line helper w/descriptor, data in descriptor. */
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gen_helper_gvec_4 *fno;
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/* The optional opcodes, if any, utilized by .fniv. */
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const TCGOpcode *opt_opc;
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/* The vector element size, if applicable. */
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uint8_t vece;
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/* Prefer i64 to v64. */
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bool prefer_i64;
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} GVecGen4i;
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void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
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void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
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uint32_t oprsz, uint32_t maxsz, const GVecGen2 *);
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uint32_t oprsz, uint32_t maxsz, const GVecGen2 *);
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void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
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void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
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@ -231,6 +250,9 @@ void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs,
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const GVecGen3i *);
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const GVecGen3i *);
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void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
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void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
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uint32_t oprsz, uint32_t maxsz, const GVecGen4 *);
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uint32_t oprsz, uint32_t maxsz, const GVecGen4 *);
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void tcg_gen_gvec_4i(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
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uint32_t oprsz, uint32_t maxsz, int64_t c,
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const GVecGen4i *);
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/* Expand a specific vector operation. */
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/* Expand a specific vector operation. */
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@ -836,6 +836,30 @@ static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(t0);
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}
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}
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static void expand_4i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
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uint32_t cofs, uint32_t oprsz, int32_t c,
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void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32,
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int32_t))
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{
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TCGv_i32 t0 = tcg_temp_new_i32();
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TCGv_i32 t1 = tcg_temp_new_i32();
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TCGv_i32 t2 = tcg_temp_new_i32();
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TCGv_i32 t3 = tcg_temp_new_i32();
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uint32_t i;
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for (i = 0; i < oprsz; i += 4) {
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tcg_gen_ld_i32(t1, cpu_env, aofs + i);
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tcg_gen_ld_i32(t2, cpu_env, bofs + i);
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tcg_gen_ld_i32(t3, cpu_env, cofs + i);
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fni(t0, t1, t2, t3, c);
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tcg_gen_st_i32(t0, cpu_env, dofs + i);
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}
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tcg_temp_free_i32(t3);
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tcg_temp_free_i32(t2);
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tcg_temp_free_i32(t1);
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tcg_temp_free_i32(t0);
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}
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/* Expand OPSZ bytes worth of two-operand operations using i64 elements. */
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/* Expand OPSZ bytes worth of two-operand operations using i64 elements. */
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static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
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static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
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bool load_dest, void (*fni)(TCGv_i64, TCGv_i64))
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bool load_dest, void (*fni)(TCGv_i64, TCGv_i64))
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@ -971,6 +995,30 @@ static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t0);
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}
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}
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static void expand_4i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
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uint32_t cofs, uint32_t oprsz, int64_t c,
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void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64,
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int64_t))
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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TCGv_i64 t2 = tcg_temp_new_i64();
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TCGv_i64 t3 = tcg_temp_new_i64();
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uint32_t i;
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for (i = 0; i < oprsz; i += 8) {
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tcg_gen_ld_i64(t1, cpu_env, aofs + i);
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tcg_gen_ld_i64(t2, cpu_env, bofs + i);
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tcg_gen_ld_i64(t3, cpu_env, cofs + i);
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fni(t0, t1, t2, t3, c);
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tcg_gen_st_i64(t0, cpu_env, dofs + i);
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}
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tcg_temp_free_i64(t3);
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tcg_temp_free_i64(t2);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(t0);
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}
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/* Expand OPSZ bytes worth of two-operand operations using host vectors. */
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/* Expand OPSZ bytes worth of two-operand operations using host vectors. */
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static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
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static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
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uint32_t oprsz, uint32_t tysz, TCGType type,
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uint32_t oprsz, uint32_t tysz, TCGType type,
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@ -1121,6 +1169,35 @@ static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
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tcg_temp_free_vec(t0);
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tcg_temp_free_vec(t0);
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}
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}
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/*
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* Expand OPSZ bytes worth of four-vector operands and an immediate operand
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* using host vectors.
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*/
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static void expand_4i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
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uint32_t bofs, uint32_t cofs, uint32_t oprsz,
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uint32_t tysz, TCGType type, int64_t c,
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void (*fni)(unsigned, TCGv_vec, TCGv_vec,
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TCGv_vec, TCGv_vec, int64_t))
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{
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TCGv_vec t0 = tcg_temp_new_vec(type);
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TCGv_vec t1 = tcg_temp_new_vec(type);
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TCGv_vec t2 = tcg_temp_new_vec(type);
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TCGv_vec t3 = tcg_temp_new_vec(type);
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uint32_t i;
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for (i = 0; i < oprsz; i += tysz) {
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tcg_gen_ld_vec(t1, cpu_env, aofs + i);
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tcg_gen_ld_vec(t2, cpu_env, bofs + i);
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tcg_gen_ld_vec(t3, cpu_env, cofs + i);
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fni(vece, t0, t1, t2, t3, c);
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tcg_gen_st_vec(t0, cpu_env, dofs + i);
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}
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tcg_temp_free_vec(t3);
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tcg_temp_free_vec(t2);
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tcg_temp_free_vec(t1);
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tcg_temp_free_vec(t0);
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}
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/* Expand a vector two-operand operation. */
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/* Expand a vector two-operand operation. */
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void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
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void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
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uint32_t oprsz, uint32_t maxsz, const GVecGen2 *g)
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uint32_t oprsz, uint32_t maxsz, const GVecGen2 *g)
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@ -1533,6 +1610,75 @@ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
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}
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}
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}
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}
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/* Expand a vector four-operand operation. */
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void tcg_gen_gvec_4i(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
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uint32_t oprsz, uint32_t maxsz, int64_t c,
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const GVecGen4i *g)
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{
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const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
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const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
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TCGType type;
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uint32_t some;
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check_size_align(oprsz, maxsz, dofs | aofs | bofs | cofs);
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check_overlap_4(dofs, aofs, bofs, cofs, maxsz);
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type = 0;
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if (g->fniv) {
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type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
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}
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switch (type) {
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case TCG_TYPE_V256:
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/*
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* Recall that ARM SVE allows vector sizes that are not a
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* power of 2, but always a multiple of 16. The intent is
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* that e.g. size == 80 would be expanded with 2x32 + 1x16.
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*/
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some = QEMU_ALIGN_DOWN(oprsz, 32);
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expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, some,
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32, TCG_TYPE_V256, c, g->fniv);
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if (some == oprsz) {
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break;
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}
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dofs += some;
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aofs += some;
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bofs += some;
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cofs += some;
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oprsz -= some;
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maxsz -= some;
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/* fallthru */
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case TCG_TYPE_V128:
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expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
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16, TCG_TYPE_V128, c, g->fniv);
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break;
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case TCG_TYPE_V64:
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expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
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8, TCG_TYPE_V64, c, g->fniv);
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break;
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case 0:
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if (g->fni8 && check_size_impl(oprsz, 8)) {
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expand_4i_i64(dofs, aofs, bofs, cofs, oprsz, c, g->fni8);
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} else if (g->fni4 && check_size_impl(oprsz, 4)) {
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expand_4i_i32(dofs, aofs, bofs, cofs, oprsz, c, g->fni4);
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} else {
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assert(g->fno != NULL);
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tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs,
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oprsz, maxsz, c, g->fno);
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oprsz = maxsz;
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}
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break;
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default:
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g_assert_not_reached();
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}
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tcg_swap_vecop_list(hold_list);
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if (oprsz < maxsz) {
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expand_clr(dofs + oprsz, maxsz - oprsz);
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}
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}
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/*
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/*
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* Expand specific vector operations.
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* Expand specific vector operations.
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*/
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*/
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