OpenE2K/qemu-e2k
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Move interrupt_request and user_mode_only to common cpu state.

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Save and restore env->interrupt_request and env->halted.



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook 2008-07-01 20:01:19 +00:00
parent a5cdf95220
commit 9656f324d2
12 changed files with 38 additions and 28 deletions
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5
cpu-defs.h
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@ -153,7 +153,8 @@ typedef struct icount_decr_u16 {
accessed */ \
target_ulong mem_io_vaddr; /* target virtual addr at which the \
memory was accessed */ \
int halted; /* TRUE if the CPU is in suspend state */ \
uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
uint32_t interrupt_request; \
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
@ -188,6 +189,8 @@ typedef struct icount_decr_u16 {
jmp_buf jmp_env; \
int exception_index; \
\
int user_mode_only; \
\
void *next_cpu; /* next CPU sharing TB cache */ \
int cpu_index; /* CPU index (informative) */ \
int running; /* Nonzero if cpu is currently running(usermode). */ \

29
exec.c
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@ -443,6 +443,33 @@ void cpu_exec_init_all(unsigned long tb_size)
#endif
}
#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
#define CPU_COMMON_SAVE_VERSION 1
static void cpu_common_save(QEMUFile *f, void *opaque)
{
CPUState *env = opaque;
qemu_put_be32s(f, &env->halted);
qemu_put_be32s(f, &env->interrupt_request);
}
static int cpu_common_load(QEMUFile *f, void *opaque, int version_id)
{
CPUState *env = opaque;
if (version_id != CPU_COMMON_SAVE_VERSION)
return -EINVAL;
qemu_get_be32s(f, &env->halted);
qemu_put_be32s(f, &env->interrupt_request);
tlb_flush(env, 1);
return 0;
}
#endif
void cpu_exec_init(CPUState *env)
{
CPUState **penv;
@ -459,6 +486,8 @@ void cpu_exec_init(CPUState *env)
env->nb_watchpoints = 0;
*penv = env;
#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION,
cpu_common_save, cpu_common_load, env);
register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
cpu_save, cpu_load, env);
#endif

2
target-alpha/cpu.h
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@ -282,11 +282,9 @@ struct CPUAlphaState {
/* Those resources are used only in Qemu core */
CPU_COMMON
int user_mode_only; /* user mode only simulation */
uint32_t hflags;
int error_code;
int interrupt_request;
uint32_t features;
uint32_t amask;

4
target-arm/cpu.h
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@ -156,10 +156,6 @@ typedef struct CPUARMState {
int (*get_irq_vector)(struct CPUARMState *);
void *irq_opaque;
/* exception/interrupt handling */
int interrupt_request;
int user_mode_only;
/* VFP coprocessor state. */
struct {
float64 regs[32];

3
target-cris/cpu.h
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@ -125,7 +125,6 @@ typedef struct CPUCRISState {
/* X flag at the time of cc snapshot. */
int cc_x;
int interrupt_request;
int interrupt_vector;
int fault_vector;
int trap_vector;
@ -156,8 +155,6 @@ typedef struct CPUCRISState {
uint32_t lo;
} tlbsets[2][4][16];
int user_mode_only;
CPU_COMMON
} CPUCRISState;

4
target-i386/cpu.h
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@ -567,8 +567,6 @@ typedef struct CPUX86State {
target_ulong exception_next_eip;
target_ulong dr[8]; /* debug registers */
uint32_t smbase;
int interrupt_request;
int user_mode_only; /* user mode only simulation */
int old_exception; /* exception in flight */
CPU_COMMON
@ -726,7 +724,7 @@ static inline int cpu_get_time_fast(void)
#define cpu_signal_handler cpu_x86_signal_handler
#define cpu_list x86_cpu_list
#define CPU_SAVE_VERSION 5
#define CPU_SAVE_VERSION 6
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel

7
target-i386/machine.c
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@ -123,7 +123,6 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_be64s(f, &env->pat);
qemu_put_be32s(f, &env->hflags2);
qemu_put_be32s(f, (uint32_t *)&env->halted);
qemu_put_be64s(f, &env->vm_hsave);
qemu_put_be64s(f, &env->vm_vmcb);
@ -169,7 +168,8 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
uint16_t fpus, fpuc, fptag, fpregs_format;
int32_t a20_mask;
if (version_id != 3 && version_id != 4 && version_id != 5)
if (version_id != 3 && version_id != 4 && version_id != 5
&& version_id != 6)
return -EINVAL;
for(i = 0; i < CPU_NB_REGS; i++)
qemu_get_betls(f, &env->regs[i]);
@ -279,7 +279,8 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
if (version_id >= 5) {
qemu_get_be64s(f, &env->pat);
qemu_get_be32s(f, &env->hflags2);
qemu_get_be32s(f, (uint32_t *)&env->halted);
if (version_id < 6)
qemu_get_be32s(f, &env->halted);
qemu_get_be64s(f, &env->vm_hsave);
qemu_get_be64s(f, &env->vm_vmcb);

4
target-m68k/cpu.h
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@ -103,10 +103,6 @@ typedef struct CPUM68KState {
/* ??? remove this. */
uint32_t t1;
/* exception/interrupt handling */
int interrupt_request;
int user_mode_only;
int pending_vector;
int pending_level;

2
target-mips/cpu.h
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@ -411,9 +411,7 @@ struct CPUMIPSState {
/* We waste some space so we can handle shadow registers like TCs. */
TCState tcs[MIPS_SHADOW_SET_MAX];
/* Qemu */
int interrupt_request;
int error_code;
int user_mode_only; /* user mode only simulation */
uint32_t hflags; /* CPU State */
/* TMASK defines different execution modes */
#define MIPS_HFLAG_TMASK 0x01FF

2
target-ppc/cpu.h
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@ -647,7 +647,6 @@ struct CPUPPCState {
uint32_t flags;
int error_code;
int interrupt_request;
uint32_t pending_interrupts;
#if !defined(CONFIG_USER_ONLY)
/* This is the IRQ controller, which is implementation dependant
@ -671,7 +670,6 @@ struct CPUPPCState {
opc_handler_t *opcodes[0x40];
/* Those resources are used only in Qemu core */
int user_mode_only; /* user mode only simulation */
target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
int mmu_idx; /* precomputed MMU index to speed up mem accesses */

2
target-sh4/cpu.h
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@ -114,8 +114,6 @@ typedef struct CPUSH4State {
uint32_t expevt; /* exception event register */
uint32_t intevt; /* interrupt event register */
int user_mode_only;
int interrupt_request;
CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
void *intc_handle;

2
target-sparc/cpu.h
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@ -215,9 +215,7 @@ typedef struct CPUSPARCState {
uint32_t pil_in; /* incoming interrupt level bitmap */
int psref; /* enable fpu */
target_ulong version;
int user_mode_only;
int interrupt_index;
int interrupt_request;
uint32_t mmu_bm;
uint32_t mmu_ctpr_mask;
uint32_t mmu_cxr_mask;