aspeed queue:
* various small cleanups and fixes * new variant of the supermicrox11-bmc machine using an ast2500-a1 SoC * at24c_eeprom extension to define eeprom contents with static arrays * ast10x0 model and test improvements * avocado update of images to use the latest -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmPiByEACgkQUaNDx8/7 7KF1nw/7BxVb8bxO5T00AnGDFNahDq3ItyisrbOkElDw18oN1eULrtZFH1UopjDE 3HKwR2nb4X7MfcLirVXXxwO1GgIxUkeCsVEY6hpg3TxDPRhPW2toNpNt/WCfFKgq ZdYdaKgkON/xHQPv6kgQzU2n9Zpuznj0CE9A3k1mAyBcCSitsvu4TW6AQBKmLgUR 9lu61onfX9XoPxZv3abuY3c3UyzevOc6BUT67dmr8naAhHLyBU+DWAW6Kg0Dtc9j p+bwxIDRimK50DJt9l13OLSAJyhrW1gMsPPGb+48OClpEOhHwq8oqRuMFpbHaQ0/ 2MMtMbavXtzBScfmLzR3yw2IwohxSXKMe+7irkJiG/hc8/gtpRATaaS+zfvS0rla QybWYtJyjmW+QUOnmBsKGwT0PWJcOd3bKtVPgPd7WGeHGVtTBOqU/svExaO+gIv8 uX1gOelEgLmLenUjc/Wp4cHgnePTBK8vG1g3IrEtcCblhwpr0e3/aJgHGgO3cQzH X9P2buwHyLzjsie9S1ebG9Ceg/VsGQpxNGISZdG+Z4c3+GYu5gcGQcqIAuFmwBnE QHSNHJXITyWjo7UuqL7e1J7vROUKn0S15V9MO/yOmZgkqubu4Gt3jGcJtIGqIBlu MFra7SiVjKBnt6PD3aKEdD9uahbqFUfmX9411ZmYUUzpfflKnCQ= =IY/i -----END PGP SIGNATURE----- Merge tag 'pull-aspeed-20230207' of https://github.com/legoater/qemu into staging aspeed queue: * various small cleanups and fixes * new variant of the supermicrox11-bmc machine using an ast2500-a1 SoC * at24c_eeprom extension to define eeprom contents with static arrays * ast10x0 model and test improvements * avocado update of images to use the latest # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmPiByEACgkQUaNDx8/7 # 7KF1nw/7BxVb8bxO5T00AnGDFNahDq3ItyisrbOkElDw18oN1eULrtZFH1UopjDE # 3HKwR2nb4X7MfcLirVXXxwO1GgIxUkeCsVEY6hpg3TxDPRhPW2toNpNt/WCfFKgq # ZdYdaKgkON/xHQPv6kgQzU2n9Zpuznj0CE9A3k1mAyBcCSitsvu4TW6AQBKmLgUR # 9lu61onfX9XoPxZv3abuY3c3UyzevOc6BUT67dmr8naAhHLyBU+DWAW6Kg0Dtc9j # p+bwxIDRimK50DJt9l13OLSAJyhrW1gMsPPGb+48OClpEOhHwq8oqRuMFpbHaQ0/ # 2MMtMbavXtzBScfmLzR3yw2IwohxSXKMe+7irkJiG/hc8/gtpRATaaS+zfvS0rla # QybWYtJyjmW+QUOnmBsKGwT0PWJcOd3bKtVPgPd7WGeHGVtTBOqU/svExaO+gIv8 # uX1gOelEgLmLenUjc/Wp4cHgnePTBK8vG1g3IrEtcCblhwpr0e3/aJgHGgO3cQzH # X9P2buwHyLzjsie9S1ebG9Ceg/VsGQpxNGISZdG+Z4c3+GYu5gcGQcqIAuFmwBnE # QHSNHJXITyWjo7UuqL7e1J7vROUKn0S15V9MO/yOmZgkqubu4Gt3jGcJtIGqIBlu # MFra7SiVjKBnt6PD3aKEdD9uahbqFUfmX9411ZmYUUzpfflKnCQ= # =IY/i # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Feb 2023 08:09:05 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20230207' of https://github.com/legoater/qemu: (25 commits) aspeed/sdmc: Drop unnecessary scu include tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4F hw/arm/aspeed_ast10x0: Map HACE peripheral hw/arm/aspeed_ast10x0: Map the secure SRAM hw/arm/aspeed_ast10x0: Map I3C peripheral hw/arm/aspeed_ast10x0: Add various unimplemented peripherals hw/misc/aspeed_hace: Do not crash if address_space_map() failed hw/watchdog/wdt_aspeed: Log unimplemented registers as UNIMP level hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize' hw/nvram/eeprom_at24c: Make reset behavior more like hardware hw/arm/aspeed: Add aspeed_eeprom.c hw/nvram/eeprom_at24c: Add init_rom field and at24c_eeprom_init_rom helper hw/arm/aspeed: Replace aspeed_eeprom_init with at24c_eeprom_init hw/arm: Extract at24c_eeprom_init helper from Aspeed and Nuvoton boards hw/core/loader: Remove declarations of option_rom_has_mr/rom_file_has_mr tests/avocado/machine_aspeed.py: Mask systemd services to speed up SDK boot tests/avocado/machine_aspeed.py: update buildroot tests m25p80: Add the is25wp256 SFPD table ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
969d09c3a6
142
hw/arm/aspeed.c
142
hw/arm/aspeed.c
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@ -14,9 +14,11 @@
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#include "hw/arm/boot.h"
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#include "hw/arm/aspeed.h"
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#include "hw/arm/aspeed_soc.h"
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#include "hw/arm/aspeed_eeprom.h"
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#include "hw/i2c/i2c_mux_pca954x.h"
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#include "hw/i2c/smbus_eeprom.h"
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#include "hw/misc/pca9552.h"
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#include "hw/nvram/eeprom_at24c.h"
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#include "hw/sensor/tmp105.h"
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#include "hw/misc/led.h"
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#include "hw/qdev-properties.h"
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@ -71,6 +73,16 @@ struct AspeedMachineState {
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
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SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
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/* TODO: Find the actual hardware value */
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#define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \
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AST2500_HW_STRAP1_DEFAULTS | \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_HW_STRAP_SPI_WIDTH | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
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/* AST2500 evb hardware value: 0xF100C2E6 */
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#define AST2500_EVB_HW_STRAP1 (( \
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AST2500_HW_STRAP1_DEFAULTS | \
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@ -429,15 +441,6 @@ static void aspeed_machine_init(MachineState *machine)
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arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
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}
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static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
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{
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I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
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DeviceState *dev = DEVICE(i2c_dev);
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qdev_prop_set_uint32(dev, "rom-size", rsize);
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i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
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}
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static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
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{
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AspeedSoCState *soc = &bmc->soc;
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@ -668,15 +671,6 @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
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eeprom_buf);
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}
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static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
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{
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I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
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DeviceState *dev = DEVICE(i2c_dev);
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qdev_prop_set_uint32(dev, "rom-size", rsize);
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i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
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}
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static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
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{
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AspeedSoCState *soc = &bmc->soc;
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@ -709,7 +703,7 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
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AspeedSoCState *soc = &bmc->soc;
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I2CSlave *i2c_mux;
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
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at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
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create_pca9552(soc, 3, 0x61);
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@ -722,9 +716,9 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
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0x4a);
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i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
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"pca9546", 0x70);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
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at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
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at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
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at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
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create_pca9552(soc, 4, 0x60);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
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@ -735,8 +729,8 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
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create_pca9552(soc, 5, 0x61);
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i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
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"pca9546", 0x70);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
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at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
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at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
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0x48);
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@ -746,10 +740,10 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
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0x4b);
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i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
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"pca9546", 0x70);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
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at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
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at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
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at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
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at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
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create_pca9552(soc, 7, 0x30);
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create_pca9552(soc, 7, 0x31);
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@ -762,15 +756,15 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
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0x48);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
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at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
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at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
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0x48);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
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0x4a);
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
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at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
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at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
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create_pca9552(soc, 8, 0x60);
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create_pca9552(soc, 8, 0x61);
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/* Bus 8: ucd90320@11 */
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@ -779,11 +773,11 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
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at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
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at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
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0x48);
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@ -791,18 +785,18 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
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0x49);
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i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
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"pca9546", 0x70);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
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at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
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at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
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create_pca9552(soc, 11, 0x60);
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
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at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
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create_pca9552(soc, 13, 0x60);
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
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at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
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create_pca9552(soc, 14, 0x60);
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
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at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
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create_pca9552(soc, 15, 0x60);
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}
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@ -846,45 +840,45 @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
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i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
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i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
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aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB);
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aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB);
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aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB);
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at24c_eeprom_init(i2c[19], 0x52, 64 * KiB);
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at24c_eeprom_init(i2c[20], 0x50, 2 * KiB);
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at24c_eeprom_init(i2c[22], 0x52, 2 * KiB);
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i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
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i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
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i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
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i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
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aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB);
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at24c_eeprom_init(i2c[8], 0x51, 64 * KiB);
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i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
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i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
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aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB);
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at24c_eeprom_init(i2c[50], 0x52, 64 * KiB);
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i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
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i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
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i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
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i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
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aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB);
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at24c_eeprom_init(i2c[65], 0x53, 64 * KiB);
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i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
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i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
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aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB);
|
||||
aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB);
|
||||
aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB);
|
||||
aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB);
|
||||
at24c_eeprom_init(i2c[68], 0x52, 64 * KiB);
|
||||
at24c_eeprom_init(i2c[69], 0x52, 64 * KiB);
|
||||
at24c_eeprom_init(i2c[70], 0x52, 64 * KiB);
|
||||
at24c_eeprom_init(i2c[71], 0x52, 64 * KiB);
|
||||
|
||||
aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB);
|
||||
at24c_eeprom_init(i2c[73], 0x53, 64 * KiB);
|
||||
i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
|
||||
i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
|
||||
aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB);
|
||||
aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB);
|
||||
aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB);
|
||||
aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB);
|
||||
aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB);
|
||||
at24c_eeprom_init(i2c[76], 0x52, 64 * KiB);
|
||||
at24c_eeprom_init(i2c[77], 0x52, 64 * KiB);
|
||||
at24c_eeprom_init(i2c[78], 0x52, 64 * KiB);
|
||||
at24c_eeprom_init(i2c[79], 0x52, 64 * KiB);
|
||||
at24c_eeprom_init(i2c[28], 0x50, 2 * KiB);
|
||||
|
||||
for (int i = 0; i < 8; i++) {
|
||||
aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
|
||||
at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
|
||||
i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
|
||||
i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
|
||||
i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
|
||||
|
|
@ -955,11 +949,14 @@ static void fby35_i2c_init(AspeedMachineState *bmc)
|
|||
i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
|
||||
i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
|
||||
|
||||
aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB);
|
||||
aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB);
|
||||
aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB);
|
||||
aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB);
|
||||
aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB);
|
||||
at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
|
||||
at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
|
||||
at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
|
||||
fby35_nic_fruid_len);
|
||||
at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
|
||||
fby35_bb_fruid_len);
|
||||
at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
|
||||
fby35_bmc_fruid_len);
|
||||
|
||||
/*
|
||||
* TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
|
||||
|
|
@ -1141,6 +1138,25 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
|
|||
mc->default_ram_size = 256 * MiB;
|
||||
}
|
||||
|
||||
static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
|
||||
void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
|
||||
amc->soc_name = "ast2500-a1";
|
||||
amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
|
||||
amc->fmc_model = "mx25l25635e";
|
||||
amc->spi_model = "mx25l25635e";
|
||||
amc->num_cs = 1;
|
||||
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
|
||||
amc->i2c_init = palmetto_bmc_i2c_init;
|
||||
mc->default_ram_size = 512 * MiB;
|
||||
mc->default_cpus = mc->min_cpus = mc->max_cpus =
|
||||
aspeed_soc_num_cpus(amc->soc_name);
|
||||
}
|
||||
|
||||
static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
|
@ -1522,6 +1538,10 @@ static const TypeInfo aspeed_machine_types[] = {
|
|||
.name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
|
||||
.parent = TYPE_ASPEED_MACHINE,
|
||||
.class_init = aspeed_machine_supermicrox11_bmc_class_init,
|
||||
}, {
|
||||
.name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
|
||||
.parent = TYPE_ASPEED_MACHINE,
|
||||
.class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
|
||||
}, {
|
||||
.name = MACHINE_TYPE_NAME("ast2500-evb"),
|
||||
.parent = TYPE_ASPEED_MACHINE,
|
||||
|
|
|
|||
|
|
@ -21,16 +21,22 @@
|
|||
|
||||
static const hwaddr aspeed_soc_ast1030_memmap[] = {
|
||||
[ASPEED_DEV_SRAM] = 0x00000000,
|
||||
[ASPEED_DEV_SBC] = 0x79000000,
|
||||
[ASPEED_DEV_SECSRAM] = 0x79000000,
|
||||
[ASPEED_DEV_IOMEM] = 0x7E600000,
|
||||
[ASPEED_DEV_PWM] = 0x7E610000,
|
||||
[ASPEED_DEV_FMC] = 0x7E620000,
|
||||
[ASPEED_DEV_SPI1] = 0x7E630000,
|
||||
[ASPEED_DEV_SPI2] = 0x7E640000,
|
||||
[ASPEED_DEV_UDC] = 0x7E6A2000,
|
||||
[ASPEED_DEV_HACE] = 0x7E6D0000,
|
||||
[ASPEED_DEV_SCU] = 0x7E6E2000,
|
||||
[ASPEED_DEV_JTAG0] = 0x7E6E4000,
|
||||
[ASPEED_DEV_JTAG1] = 0x7E6E4100,
|
||||
[ASPEED_DEV_ADC] = 0x7E6E9000,
|
||||
[ASPEED_DEV_ESPI] = 0x7E6EE000,
|
||||
[ASPEED_DEV_SBC] = 0x7E6F2000,
|
||||
[ASPEED_DEV_GPIO] = 0x7E780000,
|
||||
[ASPEED_DEV_SGPIOM] = 0x7E780500,
|
||||
[ASPEED_DEV_TIMER1] = 0x7E782000,
|
||||
[ASPEED_DEV_UART1] = 0x7E783000,
|
||||
[ASPEED_DEV_UART2] = 0x7E78D000,
|
||||
|
|
@ -48,6 +54,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
|
|||
[ASPEED_DEV_WDT] = 0x7E785000,
|
||||
[ASPEED_DEV_LPC] = 0x7E789000,
|
||||
[ASPEED_DEV_PECI] = 0x7E78B000,
|
||||
[ASPEED_DEV_I3C] = 0x7E7A0000,
|
||||
[ASPEED_DEV_I2C] = 0x7E7B0000,
|
||||
};
|
||||
|
||||
|
|
@ -78,12 +85,18 @@ static const int aspeed_soc_ast1030_irqmap[] = {
|
|||
[ASPEED_DEV_LPC] = 35,
|
||||
[ASPEED_DEV_PECI] = 38,
|
||||
[ASPEED_DEV_FMC] = 39,
|
||||
[ASPEED_DEV_ESPI] = 42,
|
||||
[ASPEED_DEV_PWM] = 44,
|
||||
[ASPEED_DEV_ADC] = 46,
|
||||
[ASPEED_DEV_SPI1] = 65,
|
||||
[ASPEED_DEV_SPI2] = 66,
|
||||
[ASPEED_DEV_I3C] = 102, /* 102 -> 105 */
|
||||
[ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
|
||||
[ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
|
||||
[ASPEED_DEV_UDC] = 9,
|
||||
[ASPEED_DEV_SGPIOM] = 51,
|
||||
[ASPEED_DEV_JTAG0] = 27,
|
||||
[ASPEED_DEV_JTAG1] = 53,
|
||||
};
|
||||
|
||||
static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
|
||||
|
|
@ -119,6 +132,8 @@ static void aspeed_soc_ast1030_init(Object *obj)
|
|||
snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
|
||||
object_initialize_child(obj, "i2c", &s->i2c, typename);
|
||||
|
||||
object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
|
||||
|
||||
snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
|
||||
object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
|
||||
|
||||
|
|
@ -151,9 +166,21 @@ static void aspeed_soc_ast1030_init(Object *obj)
|
|||
snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
|
||||
object_initialize_child(obj, "gpio", &s->gpio, typename);
|
||||
|
||||
snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
|
||||
object_initialize_child(obj, "hace", &s->hace, typename);
|
||||
|
||||
object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
|
||||
TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "sgpiom", &s->sgpiom,
|
||||
TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "jtag[0]", &s->jtag[0],
|
||||
TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "jtag[1]", &s->jtag[1],
|
||||
TYPE_UNIMPLEMENTED_DEVICE);
|
||||
}
|
||||
|
||||
static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
|
||||
|
|
@ -198,6 +225,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
|
|||
memory_region_add_subregion(s->memory,
|
||||
sc->memmap[ASPEED_DEV_SRAM],
|
||||
&s->sram);
|
||||
memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
|
||||
sc->secsram_size, &err);
|
||||
if (err != NULL) {
|
||||
error_propagate(errp, err);
|
||||
return;
|
||||
}
|
||||
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM],
|
||||
&s->secsram);
|
||||
|
||||
/* SCU */
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
|
||||
|
|
@ -220,6 +255,18 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
|
|||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
|
||||
}
|
||||
|
||||
/* I3C */
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
|
||||
return;
|
||||
}
|
||||
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
|
||||
for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
|
||||
qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
|
||||
sc->irqmap[ASPEED_DEV_I3C] + i);
|
||||
/* The AST1030 I3C controller has one IRQ per bus. */
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
|
||||
}
|
||||
|
||||
/* PECI */
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
|
||||
return;
|
||||
|
|
@ -315,17 +362,28 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
|
|||
}
|
||||
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
|
||||
|
||||
/* HACE */
|
||||
object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram),
|
||||
&error_abort);
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
|
||||
return;
|
||||
}
|
||||
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
|
||||
sc->memmap[ASPEED_DEV_HACE]);
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
|
||||
aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
|
||||
|
||||
/* Watch dog */
|
||||
for (i = 0; i < sc->wdts_num; i++) {
|
||||
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
|
||||
hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
|
||||
|
||||
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
|
||||
&error_abort);
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
|
||||
return;
|
||||
}
|
||||
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
|
||||
sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
|
||||
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
|
||||
}
|
||||
|
||||
/* GPIO */
|
||||
|
|
@ -336,6 +394,22 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
|
|||
sc->memmap[ASPEED_DEV_GPIO]);
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
|
||||
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
|
||||
|
||||
aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm",
|
||||
sc->memmap[ASPEED_DEV_PWM], 0x100);
|
||||
|
||||
aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->espi), "aspeed.espi",
|
||||
sc->memmap[ASPEED_DEV_ESPI], 0x800);
|
||||
|
||||
aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->udc), "aspeed.udc",
|
||||
sc->memmap[ASPEED_DEV_UDC], 0x1000);
|
||||
aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom",
|
||||
sc->memmap[ASPEED_DEV_SGPIOM], 0x100);
|
||||
|
||||
aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag",
|
||||
sc->memmap[ASPEED_DEV_JTAG0], 0x20);
|
||||
aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag",
|
||||
sc->memmap[ASPEED_DEV_JTAG1], 0x20);
|
||||
}
|
||||
|
||||
static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
|
||||
|
|
@ -346,9 +420,10 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
|
|||
dc->realize = aspeed_soc_ast1030_realize;
|
||||
|
||||
sc->name = "ast1030-a1";
|
||||
sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
|
||||
sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */
|
||||
sc->silicon_rev = AST1030_A1_SILICON_REV;
|
||||
sc->sram_size = 0xc0000;
|
||||
sc->secsram_size = 0x40000; /* 256 * KiB */
|
||||
sc->spis_num = 2;
|
||||
sc->ehcis_num = 0;
|
||||
sc->wdts_num = 4;
|
||||
|
|
|
|||
|
|
@ -465,14 +465,14 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
|
|||
/* Watch dog */
|
||||
for (i = 0; i < sc->wdts_num; i++) {
|
||||
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
|
||||
hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
|
||||
|
||||
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
|
||||
&error_abort);
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
|
||||
return;
|
||||
}
|
||||
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
|
||||
sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
|
||||
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
|
||||
}
|
||||
|
||||
/* RAM */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* Copyright (c) Meta Platforms, Inc. and affiliates.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*/
|
||||
|
||||
#include "aspeed_eeprom.h"
|
||||
|
||||
const uint8_t fby35_nic_fruid[] = {
|
||||
0x01, 0x00, 0x00, 0x01, 0x0f, 0x20, 0x00, 0xcf, 0x01, 0x0e, 0x19, 0xd7,
|
||||
0x5e, 0xcf, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xdd,
|
||||
0x4d, 0x65, 0x6c, 0x6c, 0x61, 0x6e, 0x6f, 0x78, 0x20, 0x43, 0x6f, 0x6e,
|
||||
0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0x20, 0x4f,
|
||||
0x43, 0x50, 0x33, 0x2e, 0x30, 0xd8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd5, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72,
|
||||
0x20, 0x30, 0x2e, 0x30, 0x32, 0xc0, 0xc0, 0xc0, 0xc1, 0x00, 0x00, 0x2f,
|
||||
0x01, 0x11, 0x19, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0xdd, 0x4d, 0x65, 0x6c, 0x6c, 0x61, 0x6e, 0x6f, 0x78, 0x20, 0x43, 0x6f,
|
||||
0x6e, 0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0x20,
|
||||
0x4f, 0x43, 0x50, 0x33, 0x2e, 0x30, 0xd5, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0xd3, 0x41, 0x39, 0x20, 0x20, 0x20, 0x20, 0x20,
|
||||
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
|
||||
0xd8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0xc0, 0xc0, 0xc0, 0xc0, 0xcd, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63,
|
||||
0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0xc1, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0xdb, 0xc0, 0x82, 0x30, 0x15, 0x79, 0x7f, 0xa6, 0x00,
|
||||
0x01, 0x18, 0x0b, 0xff, 0x08, 0x00, 0xff, 0xff, 0x64, 0x00, 0x00, 0x00,
|
||||
0x00, 0x03, 0x20, 0x01, 0xff, 0xff, 0x04, 0x46, 0x00, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0x01, 0x81, 0x09, 0x15, 0xb3, 0x10, 0x1d, 0x00,
|
||||
0x24, 0x15, 0xb3, 0x00, 0x02, 0xeb, 0x8a, 0x95, 0x5c,
|
||||
};
|
||||
|
||||
const uint8_t fby35_bb_fruid[] = {
|
||||
0x01, 0x00, 0x01, 0x03, 0x10, 0x00, 0x00, 0xeb, 0x01, 0x02, 0x17, 0xc3,
|
||||
0x4e, 0x2f, 0x41, 0xc3, 0x4e, 0x2f, 0x41, 0xc1, 0x00, 0x00, 0x00, 0x23,
|
||||
0x01, 0x0d, 0x00, 0xb6, 0xd2, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0xd5, 0x4d, 0x61, 0x6e, 0x61, 0x67, 0x65, 0x6d, 0x65, 0x6e, 0x74,
|
||||
0x20, 0x42, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x77, 0x42, 0x4d, 0x43, 0xcd,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x01, 0x0c, 0x00, 0xc6,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
|
||||
0x69, 0x74, 0x65, 0x20, 0x56, 0x33, 0x2e, 0x35, 0x20, 0x45, 0x56, 0x54,
|
||||
0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x4e, 0x2f,
|
||||
0x41, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43,
|
||||
};
|
||||
|
||||
const uint8_t fby35_bmc_fruid[] = {
|
||||
0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36,
|
||||
0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x4d,
|
||||
0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f,
|
||||
0x64, 0x75, 0x6c, 0x65, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e,
|
||||
0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
|
||||
0x69, 0x74, 0x65, 0x20, 0x56, 0x33, 0x2e, 0x35, 0x20, 0x45, 0x56, 0x54,
|
||||
0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
|
||||
0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc8, 0x43, 0x6f,
|
||||
0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45,
|
||||
};
|
||||
|
||||
const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid);
|
||||
const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid);
|
||||
const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid);
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) Meta Platforms, Inc. and affiliates.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*/
|
||||
|
||||
#ifndef ASPEED_EEPROM_H
|
||||
#define ASPEED_EEPROM_H
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
|
||||
extern const uint8_t fby35_nic_fruid[];
|
||||
extern const uint8_t fby35_bb_fruid[];
|
||||
extern const uint8_t fby35_bmc_fruid[];
|
||||
extern const size_t fby35_nic_fruid_len;
|
||||
extern const size_t fby35_bb_fruid_len;
|
||||
extern const size_t fby35_bmc_fruid_len;
|
||||
|
||||
#endif
|
||||
|
|
@ -386,14 +386,14 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
|
|||
/* Watch dog */
|
||||
for (i = 0; i < sc->wdts_num; i++) {
|
||||
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
|
||||
hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
|
||||
|
||||
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
|
||||
&error_abort);
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
|
||||
return;
|
||||
}
|
||||
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
|
||||
sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
|
||||
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
|
||||
}
|
||||
|
||||
/* RAM */
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
|
|||
'aspeed.c',
|
||||
'aspeed_ast2600.c',
|
||||
'aspeed_ast10x0.c',
|
||||
'aspeed_eeprom.c',
|
||||
'fby35.c'))
|
||||
arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
|
||||
arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
|
||||
|
|
|
|||
|
|
@ -1,6 +1,9 @@
|
|||
/*
|
||||
* SmartFusion2 SOM starter kit(from Emcraft) emulation.
|
||||
*
|
||||
* M2S-FG484 SOM hardware architecture specification:
|
||||
* https://www.emcraft.com/jdownloads/som/m2s/m2s-som-ha.pdf
|
||||
*
|
||||
* Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
|
|
@ -87,7 +90,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
|
|||
|
||||
/* Attach SPI flash to SPI0 controller */
|
||||
spi_bus = qdev_get_child_bus(dev, "spi0");
|
||||
spi_flash = qdev_new("s25sl12801");
|
||||
spi_flash = qdev_new("s25sl12801"); /* Spansion S25FL128SDPBHICO */
|
||||
qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
|
||||
if (dinfo) {
|
||||
qdev_prop_set_drive_err(spi_flash, "drive",
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include "hw/i2c/i2c_mux_pca954x.h"
|
||||
#include "hw/i2c/smbus_eeprom.h"
|
||||
#include "hw/loader.h"
|
||||
#include "hw/nvram/eeprom_at24c.h"
|
||||
#include "hw/qdev-core.h"
|
||||
#include "hw/qdev-properties.h"
|
||||
#include "qapi/error.h"
|
||||
|
|
@ -140,17 +141,6 @@ static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num)
|
|||
return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus"));
|
||||
}
|
||||
|
||||
static void at24c_eeprom_init(NPCM7xxState *soc, int bus, uint8_t addr,
|
||||
uint32_t rsize)
|
||||
{
|
||||
I2CBus *i2c_bus = npcm7xx_i2c_get_bus(soc, bus);
|
||||
I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
|
||||
DeviceState *dev = DEVICE(i2c_dev);
|
||||
|
||||
qdev_prop_set_uint32(dev, "rom-size", rsize);
|
||||
i2c_slave_realize_and_unref(i2c_dev, i2c_bus, &error_abort);
|
||||
}
|
||||
|
||||
static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine,
|
||||
NPCM7xxState *soc, const int *fan_counts)
|
||||
{
|
||||
|
|
@ -253,8 +243,8 @@ static void quanta_gsj_i2c_init(NPCM7xxState *soc)
|
|||
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c);
|
||||
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c);
|
||||
|
||||
at24c_eeprom_init(soc, 9, 0x55, 8192);
|
||||
at24c_eeprom_init(soc, 10, 0x55, 8192);
|
||||
at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 9), 0x55, 8192);
|
||||
at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 10), 0x55, 8192);
|
||||
|
||||
/*
|
||||
* i2c-11:
|
||||
|
|
@ -360,7 +350,7 @@ static void kudo_bmc_i2c_init(NPCM7xxState *soc)
|
|||
|
||||
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), TYPE_PCA9548, 0x77);
|
||||
|
||||
at24c_eeprom_init(soc, 4, 0x50, 8192); /* mbfru */
|
||||
at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 4), 0x50, 8192); /* mbfru */
|
||||
|
||||
i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 13),
|
||||
TYPE_PCA9548, 0x77);
|
||||
|
|
@ -371,7 +361,7 @@ static void kudo_bmc_i2c_init(NPCM7xxState *soc)
|
|||
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x48);
|
||||
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x49);
|
||||
|
||||
at24c_eeprom_init(soc, 14, 0x55, 8192); /* bmcfru */
|
||||
at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 14), 0x55, 8192); /* bmcfru */
|
||||
|
||||
/* TODO: Add remaining i2c devices. */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -221,7 +221,8 @@ static const FlashPartInfo known_devices[] = {
|
|||
{ INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) },
|
||||
{ INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) },
|
||||
{ INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) },
|
||||
{ INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K) },
|
||||
{ INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K),
|
||||
.sfdp_read = m25p80_sfdp_is25wp256 },
|
||||
|
||||
/* Macronix */
|
||||
{ INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
|
||||
|
|
|
|||
|
|
@ -330,3 +330,43 @@ static const uint8_t sfdp_w25q01jvq[] = {
|
|||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
};
|
||||
define_sfdp_read(w25q01jvq);
|
||||
|
||||
/*
|
||||
* Integrated Silicon Solution (ISSI)
|
||||
*/
|
||||
|
||||
static const uint8_t sfdp_is25wp256[] = {
|
||||
0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
|
||||
0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff,
|
||||
0x9d, 0x05, 0x01, 0x03, 0x80, 0x00, 0x00, 0x02,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xe5, 0x20, 0xf9, 0xff, 0xff, 0xff, 0xff, 0x0f,
|
||||
0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x80, 0xbb,
|
||||
0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
|
||||
0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
|
||||
0x10, 0xd8, 0x00, 0xff, 0x23, 0x4a, 0xc9, 0x00,
|
||||
0x82, 0xd8, 0x11, 0xce, 0xcc, 0xcd, 0x68, 0x46,
|
||||
0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xae, 0xd5, 0x5c,
|
||||
0x4a, 0x42, 0x2c, 0xff, 0xf0, 0x30, 0xfa, 0xa9,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0x50, 0x19, 0x50, 0x16, 0x9f, 0xf9, 0xc0, 0x64,
|
||||
0x8f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
};
|
||||
define_sfdp_read(is25wp256);
|
||||
|
|
|
|||
|
|
@ -26,4 +26,6 @@ uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
|
|||
|
||||
uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
|
||||
|
||||
uint8_t m25p80_sfdp_is25wp256(uint32_t addr);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -193,6 +193,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
|
|||
size_t digest_len = 0;
|
||||
int niov = 0;
|
||||
int i;
|
||||
void *haddr;
|
||||
|
||||
if (sg_mode) {
|
||||
uint32_t len = 0;
|
||||
|
|
@ -217,9 +218,13 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
|
|||
addr &= SG_LIST_ADDR_MASK;
|
||||
|
||||
plen = len & SG_LIST_LEN_MASK;
|
||||
iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false,
|
||||
MEMTXATTRS_UNSPECIFIED);
|
||||
|
||||
haddr = address_space_map(&s->dram_as, addr, &plen, false,
|
||||
MEMTXATTRS_UNSPECIFIED);
|
||||
if (haddr == NULL) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
|
||||
return;
|
||||
}
|
||||
iov[i].iov_base = haddr;
|
||||
if (acc_mode) {
|
||||
niov = gen_acc_mode_iov(s, iov, i, &plen);
|
||||
|
||||
|
|
@ -230,10 +235,14 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
|
|||
} else {
|
||||
hwaddr len = s->regs[R_HASH_SRC_LEN];
|
||||
|
||||
haddr = address_space_map(&s->dram_as, s->regs[R_HASH_SRC],
|
||||
&len, false, MEMTXATTRS_UNSPECIFIED);
|
||||
if (haddr == NULL) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
|
||||
return;
|
||||
}
|
||||
iov[0].iov_base = haddr;
|
||||
iov[0].iov_len = len;
|
||||
iov[0].iov_base = address_space_map(&s->dram_as, s->regs[R_HASH_SRC],
|
||||
&len, false,
|
||||
MEMTXATTRS_UNSPECIFIED);
|
||||
i = 1;
|
||||
|
||||
if (s->iov_count) {
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
#include "qemu/module.h"
|
||||
#include "qemu/error-report.h"
|
||||
#include "hw/misc/aspeed_sdmc.h"
|
||||
#include "hw/misc/aspeed_scu.h"
|
||||
#include "hw/qdev-properties.h"
|
||||
#include "migration/vmstate.h"
|
||||
#include "qapi/error.h"
|
||||
|
|
|
|||
|
|
@ -980,9 +980,9 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
|
|||
return size;
|
||||
}
|
||||
|
||||
/* 4 bytes for the CRC. */
|
||||
size += 4;
|
||||
crc = cpu_to_be32(crc32(~0, buf, size));
|
||||
/* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
|
||||
size += 4;
|
||||
crc_ptr = (uint8_t *) &crc;
|
||||
|
||||
/* Huge frames are truncated. */
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include "qapi/error.h"
|
||||
#include "qemu/module.h"
|
||||
#include "hw/i2c/i2c.h"
|
||||
#include "hw/nvram/eeprom_at24c.h"
|
||||
#include "hw/qdev-properties.h"
|
||||
#include "hw/qdev-properties-system.h"
|
||||
#include "sysemu/block-backend.h"
|
||||
|
|
@ -49,6 +50,9 @@ struct EEPROMState {
|
|||
uint8_t *mem;
|
||||
|
||||
BlockBackend *blk;
|
||||
|
||||
const uint8_t *init_rom;
|
||||
uint32_t init_rom_size;
|
||||
};
|
||||
|
||||
static
|
||||
|
|
@ -128,10 +132,39 @@ int at24c_eeprom_send(I2CSlave *s, uint8_t data)
|
|||
return 0;
|
||||
}
|
||||
|
||||
I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size)
|
||||
{
|
||||
return at24c_eeprom_init_rom(bus, address, rom_size, NULL, 0);
|
||||
}
|
||||
|
||||
I2CSlave *at24c_eeprom_init_rom(I2CBus *bus, uint8_t address, uint32_t rom_size,
|
||||
const uint8_t *init_rom, uint32_t init_rom_size)
|
||||
{
|
||||
EEPROMState *s;
|
||||
|
||||
s = AT24C_EE(i2c_slave_new(TYPE_AT24C_EE, address));
|
||||
|
||||
qdev_prop_set_uint32(DEVICE(s), "rom-size", rom_size);
|
||||
|
||||
/* TODO: Model init_rom with QOM properties. */
|
||||
s->init_rom = init_rom;
|
||||
s->init_rom_size = init_rom_size;
|
||||
|
||||
i2c_slave_realize_and_unref(I2C_SLAVE(s), bus, &error_abort);
|
||||
|
||||
return I2C_SLAVE(s);
|
||||
}
|
||||
|
||||
static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
EEPROMState *ee = AT24C_EE(dev);
|
||||
|
||||
if (ee->init_rom_size > ee->rsize) {
|
||||
error_setg(errp, "%s: init rom is larger than rom: %u > %u",
|
||||
TYPE_AT24C_EE, ee->init_rom_size, ee->rsize);
|
||||
return;
|
||||
}
|
||||
|
||||
if (ee->blk) {
|
||||
int64_t len = blk_getlength(ee->blk);
|
||||
|
||||
|
|
@ -151,19 +184,12 @@ static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
|
|||
}
|
||||
|
||||
ee->mem = g_malloc0(ee->rsize);
|
||||
}
|
||||
|
||||
static
|
||||
void at24c_eeprom_reset(DeviceState *state)
|
||||
{
|
||||
EEPROMState *ee = AT24C_EE(state);
|
||||
|
||||
ee->changed = false;
|
||||
ee->cur = 0;
|
||||
ee->haveaddr = 0;
|
||||
|
||||
memset(ee->mem, 0, ee->rsize);
|
||||
|
||||
if (ee->init_rom) {
|
||||
memcpy(ee->mem, ee->init_rom, MIN(ee->init_rom_size, ee->rsize));
|
||||
}
|
||||
|
||||
if (ee->blk) {
|
||||
int ret = blk_pread(ee->blk, 0, ee->rsize, ee->mem, 0);
|
||||
|
||||
|
|
@ -175,6 +201,16 @@ void at24c_eeprom_reset(DeviceState *state)
|
|||
}
|
||||
}
|
||||
|
||||
static
|
||||
void at24c_eeprom_reset(DeviceState *state)
|
||||
{
|
||||
EEPROMState *ee = AT24C_EE(state);
|
||||
|
||||
ee->changed = false;
|
||||
ee->cur = 0;
|
||||
ee->haveaddr = 0;
|
||||
}
|
||||
|
||||
static Property at24c_eeprom_props[] = {
|
||||
DEFINE_PROP_UINT32("rom-size", EEPROMState, rsize, 0),
|
||||
DEFINE_PROP_BOOL("writable", EEPROMState, writable, true),
|
||||
|
|
|
|||
|
|
@ -42,6 +42,11 @@
|
|||
#define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
|
||||
#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
|
||||
#define WDT_RESET_MASK1 (0x1c / 4)
|
||||
#define WDT_RESET_MASK2 (0x20 / 4)
|
||||
|
||||
#define WDT_SW_RESET_CTRL (0x24 / 4)
|
||||
#define WDT_SW_RESET_MASK1 (0x28 / 4)
|
||||
#define WDT_SW_RESET_MASK2 (0x2c / 4)
|
||||
|
||||
#define WDT_TIMEOUT_STATUS (0x10 / 4)
|
||||
#define WDT_TIMEOUT_CLEAR (0x14 / 4)
|
||||
|
|
@ -83,6 +88,10 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
|
|||
return s->regs[WDT_RESET_MASK1];
|
||||
case WDT_TIMEOUT_STATUS:
|
||||
case WDT_TIMEOUT_CLEAR:
|
||||
case WDT_RESET_MASK2:
|
||||
case WDT_SW_RESET_CTRL:
|
||||
case WDT_SW_RESET_MASK1:
|
||||
case WDT_SW_RESET_MASK2:
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
|
||||
__func__, offset);
|
||||
|
|
@ -190,6 +199,10 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
|
|||
|
||||
case WDT_TIMEOUT_STATUS:
|
||||
case WDT_TIMEOUT_CLEAR:
|
||||
case WDT_RESET_MASK2:
|
||||
case WDT_SW_RESET_CTRL:
|
||||
case WDT_SW_RESET_MASK1:
|
||||
case WDT_SW_RESET_MASK2:
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
|
||||
__func__, offset);
|
||||
|
|
@ -260,6 +273,7 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
|
|||
{
|
||||
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
||||
AspeedWDTState *s = ASPEED_WDT(dev);
|
||||
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(dev);
|
||||
|
||||
assert(s->scu);
|
||||
|
||||
|
|
@ -271,7 +285,7 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
|
|||
s->pclk_freq = PCLK_HZ;
|
||||
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
|
||||
TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
|
||||
TYPE_ASPEED_WDT, awc->iosize);
|
||||
sysbus_init_mmio(sbd, &s->iomem);
|
||||
}
|
||||
|
||||
|
|
@ -309,7 +323,7 @@ static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data)
|
|||
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
|
||||
|
||||
dc->desc = "ASPEED 2400 Watchdog Controller";
|
||||
awc->offset = 0x20;
|
||||
awc->iosize = 0x20;
|
||||
awc->ext_pulse_width_mask = 0xff;
|
||||
awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
|
||||
awc->wdt_reload = aspeed_wdt_reload;
|
||||
|
|
@ -346,7 +360,7 @@ static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data)
|
|||
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
|
||||
|
||||
dc->desc = "ASPEED 2500 Watchdog Controller";
|
||||
awc->offset = 0x20;
|
||||
awc->iosize = 0x20;
|
||||
awc->ext_pulse_width_mask = 0xfffff;
|
||||
awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
|
||||
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
|
||||
|
|
@ -369,7 +383,7 @@ static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data)
|
|||
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
|
||||
|
||||
dc->desc = "ASPEED 2600 Watchdog Controller";
|
||||
awc->offset = 0x40;
|
||||
awc->iosize = 0x40;
|
||||
awc->ext_pulse_width_mask = 0xfffff; /* TODO */
|
||||
awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
|
||||
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
|
||||
|
|
@ -392,7 +406,7 @@ static void aspeed_1030_wdt_class_init(ObjectClass *klass, void *data)
|
|||
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
|
||||
|
||||
dc->desc = "ASPEED 1030 Watchdog Controller";
|
||||
awc->offset = 0x80;
|
||||
awc->iosize = 0x80;
|
||||
awc->ext_pulse_width_mask = 0xfffff; /* TODO */
|
||||
awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
|
||||
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@
|
|||
#define ASPEED_CPUS_NUM 2
|
||||
#define ASPEED_MACS_NUM 4
|
||||
#define ASPEED_UARTS_NUM 13
|
||||
#define ASPEED_JTAG_NUM 2
|
||||
|
||||
struct AspeedSoCState {
|
||||
/*< private >*/
|
||||
|
|
@ -70,6 +71,7 @@ struct AspeedSoCState {
|
|||
AspeedSMCState spi[ASPEED_SPIS_NUM];
|
||||
EHCISysBusState ehci[ASPEED_EHCIS_NUM];
|
||||
AspeedSBCState sbc;
|
||||
MemoryRegion secsram;
|
||||
UnimplementedDeviceState sbc_unimplemented;
|
||||
AspeedSDMCState sdmc;
|
||||
AspeedWDTState wdt[ASPEED_WDTS_NUM];
|
||||
|
|
@ -87,6 +89,11 @@ struct AspeedSoCState {
|
|||
UnimplementedDeviceState video;
|
||||
UnimplementedDeviceState emmc_boot_controller;
|
||||
UnimplementedDeviceState dpmcu;
|
||||
UnimplementedDeviceState pwm;
|
||||
UnimplementedDeviceState espi;
|
||||
UnimplementedDeviceState udc;
|
||||
UnimplementedDeviceState sgpiom;
|
||||
UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
|
||||
};
|
||||
|
||||
#define TYPE_ASPEED_SOC "aspeed-soc"
|
||||
|
|
@ -99,6 +106,7 @@ struct AspeedSoCClass {
|
|||
const char *cpu_type;
|
||||
uint32_t silicon_rev;
|
||||
uint64_t sram_size;
|
||||
uint64_t secsram_size;
|
||||
int spis_num;
|
||||
int ehcis_num;
|
||||
int wdts_num;
|
||||
|
|
@ -137,6 +145,7 @@ enum {
|
|||
ASPEED_DEV_SCU,
|
||||
ASPEED_DEV_ADC,
|
||||
ASPEED_DEV_SBC,
|
||||
ASPEED_DEV_SECSRAM,
|
||||
ASPEED_DEV_EMMC_BC,
|
||||
ASPEED_DEV_VIDEO,
|
||||
ASPEED_DEV_SRAM,
|
||||
|
|
@ -174,6 +183,11 @@ enum {
|
|||
ASPEED_DEV_DPMCU,
|
||||
ASPEED_DEV_DP,
|
||||
ASPEED_DEV_I3C,
|
||||
ASPEED_DEV_ESPI,
|
||||
ASPEED_DEV_UDC,
|
||||
ASPEED_DEV_SGPIOM,
|
||||
ASPEED_DEV_JTAG0,
|
||||
ASPEED_DEV_JTAG1,
|
||||
};
|
||||
|
||||
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
|
||||
|
|
|
|||
|
|
@ -251,9 +251,6 @@ void pstrcpy_targphys(const char *name,
|
|||
hwaddr dest, int buf_size,
|
||||
const char *source);
|
||||
|
||||
extern bool option_rom_has_mr;
|
||||
extern bool rom_file_has_mr;
|
||||
|
||||
ssize_t rom_add_file(const char *file, const char *fw_dir,
|
||||
hwaddr addr, int32_t bootindex,
|
||||
bool option_rom, MemoryRegion *mr, AddressSpace *as);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright (c) Meta Platforms, Inc. and affiliates.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*/
|
||||
|
||||
#ifndef EEPROM_AT24C_H
|
||||
#define EEPROM_AT24C_H
|
||||
|
||||
#include "hw/i2c/i2c.h"
|
||||
|
||||
/*
|
||||
* Create and realize an AT24C EEPROM device on the heap.
|
||||
* @bus: I2C bus to put it on
|
||||
* @address: I2C address of the EEPROM slave when put on a bus
|
||||
* @rom_size: size of the EEPROM
|
||||
*
|
||||
* Create the device state structure, initialize it, put it on the specified
|
||||
* @bus, and drop the reference to it (the device is realized).
|
||||
*/
|
||||
I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size);
|
||||
|
||||
|
||||
/*
|
||||
* Create and realize an AT24C EEPROM device on the heap with initial data.
|
||||
* @bus: I2C bus to put it on
|
||||
* @address: I2C address of the EEPROM slave when put on a bus
|
||||
* @rom_size: size of the EEPROM
|
||||
* @init_rom: Array of bytes to initialize EEPROM memory with
|
||||
* @init_rom_size: Size of @init_rom, must be less than or equal to @rom_size
|
||||
*
|
||||
* Create the device state structure, initialize it, put it on the specified
|
||||
* @bus, and drop the reference to it (the device is realized). Copies the data
|
||||
* from @init_rom to the beginning of the EEPROM memory buffer.
|
||||
*/
|
||||
I2CSlave *at24c_eeprom_init_rom(I2CBus *bus, uint8_t address, uint32_t rom_size,
|
||||
const uint8_t *init_rom, uint32_t init_rom_size);
|
||||
|
||||
#endif
|
||||
|
|
@ -21,7 +21,7 @@ OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT)
|
|||
#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
|
||||
#define TYPE_ASPEED_1030_WDT TYPE_ASPEED_WDT "-ast1030"
|
||||
|
||||
#define ASPEED_WDT_REGS_MAX (0x20 / 4)
|
||||
#define ASPEED_WDT_REGS_MAX (0x30 / 4)
|
||||
|
||||
struct AspeedWDTState {
|
||||
/*< private >*/
|
||||
|
|
@ -40,7 +40,7 @@ struct AspeedWDTState {
|
|||
struct AspeedWDTClass {
|
||||
SysBusDeviceClass parent_class;
|
||||
|
||||
uint32_t offset;
|
||||
uint32_t iosize;
|
||||
uint32_t ext_pulse_width_mask;
|
||||
uint32_t reset_ctrl_reg;
|
||||
void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
|
||||
|
|
|
|||
|
|
@ -30,6 +30,11 @@ Round up to next power of 2
|
|||
def pow2ceil(x):
|
||||
return 1 if x == 0 else 2**(x - 1).bit_length()
|
||||
|
||||
def file_truncate(path, size):
|
||||
if size != os.path.getsize(path):
|
||||
with open(path, 'ab+') as fd:
|
||||
fd.truncate(size)
|
||||
|
||||
"""
|
||||
Expand file size to next power of 2
|
||||
"""
|
||||
|
|
@ -395,6 +400,8 @@ class BootLinuxConsole(LinuxKernelTest):
|
|||
spi_hash = '65523a1835949b6f4553be96dec1b6a38fb05501'
|
||||
spi_path = self.fetch_asset(spi_url, asset_hash=spi_hash)
|
||||
|
||||
file_truncate(spi_path, 16 << 20) # Spansion S25FL128SDPBHICO is 16 MiB
|
||||
|
||||
self.vm.set_console()
|
||||
kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE
|
||||
self.vm.add_args('-kernel', uboot_path,
|
||||
|
|
@ -1098,18 +1105,18 @@ class BootLinuxConsole(LinuxKernelTest):
|
|||
def test_arm_ast2600_debian(self):
|
||||
"""
|
||||
:avocado: tags=arch:arm
|
||||
:avocado: tags=machine:tacoma-bmc
|
||||
:avocado: tags=machine:rainier-bmc
|
||||
"""
|
||||
deb_url = ('http://snapshot.debian.org/archive/debian/'
|
||||
'20210302T203551Z/'
|
||||
'20220606T211338Z/'
|
||||
'pool/main/l/linux/'
|
||||
'linux-image-5.10.0-3-armmp_5.10.13-1_armhf.deb')
|
||||
deb_hash = 'db40d32fe39255d05482bea48d72467b67d6225bb2a2a4d6f618cb8976f1e09e'
|
||||
'linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb')
|
||||
deb_hash = '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660c8abe4dcdc0e'
|
||||
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash,
|
||||
algorithm='sha256')
|
||||
kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.10.0-3-armmp')
|
||||
kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.17.0-2-armmp')
|
||||
dtb_path = self.extract_from_deb(deb_path,
|
||||
'/usr/lib/linux-image-5.10.0-3-armmp/aspeed-bmc-opp-tacoma.dtb')
|
||||
'/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainier.dtb')
|
||||
|
||||
self.vm.set_console()
|
||||
self.vm.add_args('-kernel', kernel_path,
|
||||
|
|
|
|||
|
|
@ -22,10 +22,11 @@ class AST1030Machine(QemuSystemTest):
|
|||
|
||||
timeout = 10
|
||||
|
||||
def test_ast1030_zephyros(self):
|
||||
def test_ast1030_zephyros_1_04(self):
|
||||
"""
|
||||
:avocado: tags=arch:arm
|
||||
:avocado: tags=machine:ast1030-evb
|
||||
:avocado: tags=os:zephyr
|
||||
"""
|
||||
tar_url = ('https://github.com/AspeedTech-BMC'
|
||||
'/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip')
|
||||
|
|
@ -41,6 +42,44 @@ class AST1030Machine(QemuSystemTest):
|
|||
exec_command_and_wait_for_pattern(self, "help",
|
||||
"Available commands")
|
||||
|
||||
def test_ast1030_zephyros_1_07(self):
|
||||
"""
|
||||
:avocado: tags=arch:arm
|
||||
:avocado: tags=machine:ast1030-evb
|
||||
:avocado: tags=os:zephyr
|
||||
"""
|
||||
tar_url = ('https://github.com/AspeedTech-BMC'
|
||||
'/zephyr/releases/download/v00.01.07/ast1030-evb-demo.zip')
|
||||
tar_hash = '40ac87eabdcd3b3454ce5aad11fedc72a33ecda2'
|
||||
tar_path = self.fetch_asset(tar_url, asset_hash=tar_hash)
|
||||
archive.extract(tar_path, self.workdir)
|
||||
kernel_file = self.workdir + "/ast1030-evb-demo/zephyr.bin"
|
||||
self.vm.set_console()
|
||||
self.vm.add_args('-kernel', kernel_file,
|
||||
'-nographic')
|
||||
self.vm.launch()
|
||||
wait_for_console_pattern(self, "Booting Zephyr OS")
|
||||
for shell_cmd in [
|
||||
'kernel stacks',
|
||||
'otp info conf',
|
||||
'otp info scu',
|
||||
'hwinfo devid',
|
||||
'crypto aes256_cbc_vault',
|
||||
'random get',
|
||||
'jtag JTAG1 sw_xfer high TMS',
|
||||
'adc ADC0 resolution 12',
|
||||
'adc ADC0 read 42',
|
||||
'adc ADC1 read 69',
|
||||
'i2c scan I2C_0',
|
||||
'i3c attach I3C_0',
|
||||
'hash test',
|
||||
'kernel uptime',
|
||||
'kernel reboot warm',
|
||||
'kernel uptime',
|
||||
'kernel reboot cold',
|
||||
'kernel uptime',
|
||||
]: exec_command_and_wait_for_pattern(self, shell_cmd, "uart:~$")
|
||||
|
||||
class AST2x00Machine(QemuSystemTest):
|
||||
|
||||
timeout = 90
|
||||
|
|
@ -123,8 +162,8 @@ class AST2x00Machine(QemuSystemTest):
|
|||
"""
|
||||
|
||||
image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
|
||||
'images/ast2500-evb/buildroot-2022.05/flash.img')
|
||||
image_hash = ('549db6e9d8cdaf4367af21c36385a68bb465779c18b5e37094fc7343decccd3f')
|
||||
'images/ast2500-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
|
||||
image_hash = ('f96d11db521fe7a2787745e9e391225deeeec3318ee0fc07c8b799b8833dd474')
|
||||
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
|
||||
algorithm='sha256')
|
||||
|
||||
|
|
@ -151,8 +190,8 @@ class AST2x00Machine(QemuSystemTest):
|
|||
"""
|
||||
|
||||
image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
|
||||
'images/ast2600-evb/buildroot-2022.05/flash.img')
|
||||
image_hash = ('6cc9e7d128fd4fa1fd01c883af67593cae8072c3239a0b8b6ace857f3538a92d')
|
||||
'images/ast2600-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
|
||||
image_hash = ('e598d86e5ea79671ca8b59212a326c911bc8bea728dec1a1f5390d717a28bb8b')
|
||||
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
|
||||
algorithm='sha256')
|
||||
|
||||
|
|
@ -183,7 +222,14 @@ class AST2x00Machine(QemuSystemTest):
|
|||
|
||||
class AST2x00MachineSDK(QemuSystemTest):
|
||||
|
||||
EXTRA_BOOTARGS = ' quiet'
|
||||
EXTRA_BOOTARGS = (
|
||||
'quiet '
|
||||
'systemd.mask=org.openbmc.HostIpmi.service '
|
||||
'systemd.mask=xyz.openbmc_project.Chassis.Control.Power@0.service '
|
||||
'systemd.mask=modprobe@fuse.service '
|
||||
'systemd.mask=rngd.service '
|
||||
'systemd.mask=obmc-console@ttyS2.service '
|
||||
)
|
||||
|
||||
# FIXME: Although these tests boot a whole distro they are still
|
||||
# slower than comparable machine models. There may be some
|
||||
|
|
@ -208,7 +254,7 @@ class AST2x00MachineSDK(QemuSystemTest):
|
|||
interrupt_interactive_console_until_pattern(
|
||||
self, 'Hit any key to stop autoboot:', 'ast#')
|
||||
exec_command_and_wait_for_pattern(
|
||||
self, 'setenv bootargs ${bootargs}' + self.EXTRA_BOOTARGS, 'ast#')
|
||||
self, 'setenv bootargs ${bootargs} ' + self.EXTRA_BOOTARGS, 'ast#')
|
||||
exec_command_and_wait_for_pattern(
|
||||
self, 'boot', '## Loading kernel from FIT Image')
|
||||
self.wait_for_console_pattern('Starting kernel ...')
|
||||
|
|
|
|||
Loading…
Reference in New Issue