target/riscv/csr.c: simplify mctr()
Use riscv_cpu_cfg() to retrieve pmu_num. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230224174520.92490-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -165,8 +165,7 @@ static RISCVException ctr32(CPURISCVState *env, int csrno)
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#if !defined(CONFIG_USER_ONLY)
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static RISCVException mctr(CPURISCVState *env, int csrno)
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{
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CPUState *cs = env_cpu(env);
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RISCVCPU *cpu = RISCV_CPU(cs);
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int pmu_num = riscv_cpu_cfg(env)->pmu_num;
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int ctr_index;
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int base_csrno = CSR_MHPMCOUNTER3;
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@ -175,7 +174,7 @@ static RISCVException mctr(CPURISCVState *env, int csrno)
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base_csrno += 0x80;
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}
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ctr_index = csrno - base_csrno;
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if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) {
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if (!pmu_num || ctr_index >= pmu_num) {
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/* The PMU is not enabled or counter is out of range*/
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return RISCV_EXCP_ILLEGAL_INST;
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}
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