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target/mips: Use decode_ase_msa() generated from decodetree 

Now that we can decode the MSA ASE with decode_ase_msa(),
use it and remove the previous code, now unreachable.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-21-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
This commit is contained in:
Philippe Mathieu-Daudé 2020-11-30 14:10:32 +01:00
parent c7a9ef7517
commit 96e5b4c758
3 changed files with 11 additions and 62 deletions
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29
target/mips/msa_translate.c
View File

@ -412,33 +412,6 @@ static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
}
void gen_msa_branch(DisasContext *ctx, uint32_t op1)
{
uint8_t df = (ctx->opcode >> 21) & 0x3;
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
int64_t s16 = (int16_t)ctx->opcode;
switch (op1) {
case OPC_BZ_V:
case OPC_BNZ_V:
gen_msa_BxZ_V(ctx, wt, s16, (op1 == OPC_BZ_V) ?
TCG_COND_EQ : TCG_COND_NE);
break;
case OPC_BZ_B:
case OPC_BZ_H:
case OPC_BZ_W:
case OPC_BZ_D:
gen_msa_BxZ(ctx, df, wt, s16, false);
break;
case OPC_BNZ_B:
case OPC_BNZ_H:
case OPC_BNZ_W:
case OPC_BNZ_D:
gen_msa_BxZ(ctx, df, wt, s16, true);
break;
}
}
static void gen_msa_i8(DisasContext *ctx)
{
#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
@ -2188,7 +2161,7 @@ static void gen_msa_vec(DisasContext *ctx)
}
}
void gen_msa(DisasContext *ctx)
static void gen_msa(DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;

32
target/mips/translate.c
View File

@ -6,6 +6,7 @@
* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
* Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
* Copyright (c) 2020 Philippe Mathieu-Daudé
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@ -135,8 +136,6 @@ enum {
OPC_JIALC = (0x3E << 26),
/* MDMX ASE specific */
OPC_MDMX = (0x1E << 26),
/* MSA ASE, same as MDMX */
OPC_MSA = OPC_MDMX,
/* Cache and prefetch */
OPC_CACHE = (0x2F << 26),
OPC_PREF = (0x33 << 26),
@ -28827,21 +28826,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
}
case OPC_BZ_V:
case OPC_BNZ_V:
case OPC_BZ_B:
case OPC_BZ_H:
case OPC_BZ_W:
case OPC_BZ_D:
case OPC_BNZ_B:
case OPC_BNZ_H:
case OPC_BNZ_W:
case OPC_BNZ_D:
if (ase_msa_available(env)) {
gen_msa_branch(ctx, op1);
break;
}
/* fall through */
default:
MIPS_INVAL("cp1");
gen_reserved_instruction(ctx);
@ -29023,16 +29007,13 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
}
break;
case OPC_MSA: /* OPC_MDMX */
case OPC_MDMX: /* MMI_OPC_LQ */
if (ctx->insn_flags & INSN_R5900) {
#if defined(TARGET_MIPS64)
gen_mmi_lq(env, ctx); /* MMI_OPC_LQ */
gen_mmi_lq(env, ctx);
#endif
} else {
/* MDMX: Not implemented. */
if (ase_msa_available(env)) {
gen_msa(ctx);
}
}
break;
case OPC_PCREL:
@ -29065,6 +29046,13 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_set_label(l1);
}
/* Transition to the auto-generated decoder. */
/* ISA extensions */
if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
return;
}
if (decode_opc_legacy(env, ctx)) {
return;
}

12
target/mips/translate.h
View File

@ -82,8 +82,6 @@ enum {
OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
OPC_BZ_V = (0x0B << 21) | OPC_CP1,
OPC_BNZ_V = (0x0F << 21) | OPC_CP1,
OPC_S_FMT = (FMT_S << 21) | OPC_CP1,
OPC_D_FMT = (FMT_D << 21) | OPC_CP1,
OPC_E_FMT = (FMT_E << 21) | OPC_CP1,
@ -93,14 +91,6 @@ enum {
OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
OPC_BC1EQZ = (0x09 << 21) | OPC_CP1,
OPC_BC1NEZ = (0x0D << 21) | OPC_CP1,
OPC_BZ_B = (0x18 << 21) | OPC_CP1,
OPC_BZ_H = (0x19 << 21) | OPC_CP1,
OPC_BZ_W = (0x1A << 21) | OPC_CP1,
OPC_BZ_D = (0x1B << 21) | OPC_CP1,
OPC_BNZ_B = (0x1C << 21) | OPC_CP1,
OPC_BNZ_H = (0x1D << 21) | OPC_CP1,
OPC_BNZ_W = (0x1E << 21) | OPC_CP1,
OPC_BNZ_D = (0x1F << 21) | OPC_CP1,
};
#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F))
@ -174,8 +164,6 @@ extern TCGv bcond;
/* MSA */
void msa_translate_init(void);
void gen_msa(DisasContext *ctx);
void gen_msa_branch(DisasContext *ctx, uint32_t op1);
/* decodetree generated */
bool decode_ase_msa(DisasContext *ctx, uint32_t insn);