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target/ppc: added the instructions LXVP and STXVP

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Implemented the instructions lxvp and stxvp using decodetree

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-15-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Lucas Mateus Castro (alqotel) 2021-11-04 09:37:08 -03:00 committed by David Gibson
parent 70426b5bb7
commit 96fa263247
2 changed files with 48 additions and 12 deletions
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5
target/ppc/insn32.decode
View File

@ -31,6 +31,9 @@
%dq_rt_tsx 3:1 21:5 %dq_rt_tsx 3:1 21:5
@DQ_TSX ...... ..... ra:5 ............ .... &D si=%dq_si rt=%dq_rt_tsx @DQ_TSX ...... ..... ra:5 ............ .... &D si=%dq_si rt=%dq_rt_tsx
%rt_tsxp 21:1 22:4 !function=times_2
@DQ_TSXP ...... ..... ra:5 ............ .... &D si=%dq_si rt=%rt_tsxp
%ds_si 2:s14 !function=times_4 %ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si @DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
@ -396,5 +399,7 @@ VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
LXV 111101 ..... ..... ............ . 001 @DQ_TSX LXV 111101 ..... ..... ............ . 001 @DQ_TSX
STXV 111101 ..... ..... ............ . 101 @DQ_TSX STXV 111101 ..... ..... ............ . 101 @DQ_TSX
LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP
STXVP 000110 ..... ..... ............ 0001 @DQ_TSXP
LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX

53
target/ppc/translate/vsx-impl.c.inc
View File

@ -1945,11 +1945,12 @@ static void gen_xvxsigdp(DisasContext *ctx)
} }
static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ, static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
int rt, bool store) int rt, bool store, bool paired)
{ {
TCGv ea; TCGv ea;
TCGv_i64 xt; TCGv_i64 xt;
MemOp mop; MemOp mop;
int rt1, rt2;
xt = tcg_temp_new_i64(); xt = tcg_temp_new_i64();
@ -1958,18 +1959,42 @@ static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
gen_set_access_type(ctx, ACCESS_INT); gen_set_access_type(ctx, ACCESS_INT);
ea = do_ea_calc(ctx, ra, displ); ea = do_ea_calc(ctx, ra, displ);
if (paired && ctx->le_mode) {
rt1 = rt + 1;
rt2 = rt;
} else {
rt1 = rt;
rt2 = rt + 1;
}
if (store) { if (store) {
get_cpu_vsr(xt, rt, !ctx->le_mode); get_cpu_vsr(xt, rt1, !ctx->le_mode);
tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop); tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
gen_addr_add(ctx, ea, ea, 8); gen_addr_add(ctx, ea, ea, 8);
get_cpu_vsr(xt, rt, ctx->le_mode); get_cpu_vsr(xt, rt1, ctx->le_mode);
tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop); tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
if (paired) {
gen_addr_add(ctx, ea, ea, 8);
get_cpu_vsr(xt, rt2, !ctx->le_mode);
tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
gen_addr_add(ctx, ea, ea, 8);
get_cpu_vsr(xt, rt2, ctx->le_mode);
tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
}
} else { } else {
tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop); tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
set_cpu_vsr(rt, xt, !ctx->le_mode); set_cpu_vsr(rt1, xt, !ctx->le_mode);
gen_addr_add(ctx, ea, ea, 8); gen_addr_add(ctx, ea, ea, 8);
tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop); tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
set_cpu_vsr(rt, xt, ctx->le_mode); set_cpu_vsr(rt1, xt, ctx->le_mode);
if (paired) {
gen_addr_add(ctx, ea, ea, 8);
tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
set_cpu_vsr(rt2, xt, !ctx->le_mode);
gen_addr_add(ctx, ea, ea, 8);
tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
set_cpu_vsr(rt2, xt, ctx->le_mode);
}
} }
tcg_temp_free(ea); tcg_temp_free(ea);
@ -1977,17 +2002,21 @@ static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
return true; return true;
} }
static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store) static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired)
{ {
if (paired) {
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
} else {
REQUIRE_INSNS_FLAGS2(ctx, ISA300); REQUIRE_INSNS_FLAGS2(ctx, ISA300);
}
if (a->rt >= 32) { if (paired || a->rt >= 32) {
REQUIRE_VSX(ctx); REQUIRE_VSX(ctx);
} else { } else {
REQUIRE_VECTOR(ctx); REQUIRE_VECTOR(ctx);
} }
return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store); return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store, paired);
} }
static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store) static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store)
@ -2000,11 +2029,13 @@ static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store)
REQUIRE_VECTOR(ctx); REQUIRE_VECTOR(ctx);
} }
return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store); return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, false);
} }
TRANS(STXV, do_lstxv_D, true) TRANS(STXV, do_lstxv_D, true, false)
TRANS(LXV, do_lstxv_D, false) TRANS(LXV, do_lstxv_D, false, false)
TRANS(STXVP, do_lstxv_D, true, true)
TRANS(LXVP, do_lstxv_D, false, true)
TRANS(STXVX, do_lstxv_X, true) TRANS(STXVX, do_lstxv_X, true)
TRANS(LXVX, do_lstxv_X, false) TRANS(LXVX, do_lstxv_X, false)