bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) block
At present only the core UART functions (data path for tx/rx) are implemented, which is enough for UEFI to boot. The following features/registers are unimplemented: * Line/modem control * Scratch register * Extra control * Baudrate * SPI interfaces Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1457467526-8840-3-git-send-email-Andrew.Baumann@microsoft.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Andrew Baumann
Peter Maydell
parent
a2a8dfa8d8
commit
97398d900c
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@ -12,6 +12,7 @@
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#include "hw/arm/bcm2835_peripherals.h"
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#include "hw/misc/bcm2835_mbox_defs.h"
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#include "hw/arm/raspi_platform.h"
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#include "sysemu/char.h"
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/* Peripheral base address on the VC (GPU) system bus */
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#define BCM2835_VC_PERI_BASE 0x7e000000
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@ -48,6 +49,11 @@ static void bcm2835_peripherals_init(Object *obj)
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object_property_add_child(obj, "uart0", OBJECT(s->uart0), NULL);
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qdev_set_parent_bus(DEVICE(s->uart0), sysbus_get_default());
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/* AUX / UART1 */
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object_initialize(&s->aux, sizeof(s->aux), TYPE_BCM2835_AUX);
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object_property_add_child(obj, "aux", OBJECT(&s->aux), NULL);
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qdev_set_parent_bus(DEVICE(&s->aux), sysbus_get_default());
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/* Mailboxes */
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object_initialize(&s->mboxes, sizeof(s->mboxes), TYPE_BCM2835_MBOX);
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object_property_add_child(obj, "mbox", OBJECT(&s->mboxes), NULL);
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@ -79,6 +85,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
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MemoryRegion *ram;
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Error *err = NULL;
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uint32_t ram_size;
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CharDriverState *chr;
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int n;
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obj = object_property_get_link(OBJECT(dev), "ram", &err);
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@ -131,6 +138,29 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
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qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
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INTERRUPT_UART));
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/* AUX / UART1 */
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/* TODO: don't call qemu_char_get_next_serial() here, instead set
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* chardev properties for each uart at the board level, once pl011
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* (uart0) has been updated to avoid qemu_char_get_next_serial()
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*/
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chr = qemu_char_get_next_serial();
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if (chr == NULL) {
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chr = qemu_chr_new("bcm2835.uart1", "null", NULL);
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}
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qdev_prop_set_chr(DEVICE(&s->aux), "chardev", chr);
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object_property_set_bool(OBJECT(&s->aux), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->peri_mr, UART1_OFFSET,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->aux), 0));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->aux), 0,
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qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
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INTERRUPT_AUX));
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/* Mailboxes */
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object_property_set_bool(OBJECT(&s->mboxes), true, "realized", &err);
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if (err) {
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@ -203,6 +233,8 @@ static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data)
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = bcm2835_peripherals_realize;
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/* Reason: realize() method uses qemu_char_get_next_serial() */
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dc->cannot_instantiate_with_device_add_yet = true;
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}
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static const TypeInfo bcm2835_peripherals_type_info = {
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@ -16,6 +16,7 @@ obj-$(CONFIG_SH4) += sh_serial.o
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obj-$(CONFIG_PSERIES) += spapr_vty.o
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obj-$(CONFIG_DIGIC) += digic-uart.o
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obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o
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obj-$(CONFIG_RASPI) += bcm2835_aux.o
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common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
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common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o
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@ -0,0 +1,316 @@
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/*
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* BCM2835 (Raspberry Pi / Pi 2) Aux block (mini UART and SPI).
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* Copyright (c) 2015, Microsoft
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* Written by Andrew Baumann
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* Based on pl011.c, copyright terms below:
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*
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* Arm PrimeCell PL011 UART
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*
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*
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* At present only the core UART functions (data path for tx/rx) are
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* implemented. The following features/registers are unimplemented:
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* - Line/modem control
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* - Scratch register
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* - Extra control
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* - Baudrate
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* - SPI interfaces
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*/
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#include "qemu/osdep.h"
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#include "hw/char/bcm2835_aux.h"
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#define AUX_IRQ 0x0
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#define AUX_ENABLES 0x4
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#define AUX_MU_IO_REG 0x40
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#define AUX_MU_IER_REG 0x44
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#define AUX_MU_IIR_REG 0x48
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#define AUX_MU_LCR_REG 0x4c
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#define AUX_MU_MCR_REG 0x50
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#define AUX_MU_LSR_REG 0x54
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#define AUX_MU_MSR_REG 0x58
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#define AUX_MU_SCRATCH 0x5c
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#define AUX_MU_CNTL_REG 0x60
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#define AUX_MU_STAT_REG 0x64
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#define AUX_MU_BAUD_REG 0x68
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/* bits in IER/IIR registers */
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#define TX_INT 0x1
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#define RX_INT 0x2
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static void bcm2835_aux_update(BCM2835AuxState *s)
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{
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/* signal an interrupt if either:
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* 1. rx interrupt is enabled and we have a non-empty rx fifo, or
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* 2. the tx interrupt is enabled (since we instantly drain the tx fifo)
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*/
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s->iir = 0;
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if ((s->ier & RX_INT) && s->read_count != 0) {
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s->iir |= RX_INT;
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}
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if (s->ier & TX_INT) {
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s->iir |= TX_INT;
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}
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qemu_set_irq(s->irq, s->iir != 0);
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}
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static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size)
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{
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BCM2835AuxState *s = opaque;
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uint32_t c, res;
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switch (offset) {
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case AUX_IRQ:
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return s->iir != 0;
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case AUX_ENABLES:
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return 1; /* mini UART permanently enabled */
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case AUX_MU_IO_REG:
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/* "DLAB bit set means access baudrate register" is NYI */
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c = s->read_fifo[s->read_pos];
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if (s->read_count > 0) {
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s->read_count--;
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if (++s->read_pos == BCM2835_AUX_RX_FIFO_LEN) {
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s->read_pos = 0;
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}
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}
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if (s->chr) {
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qemu_chr_accept_input(s->chr);
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}
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bcm2835_aux_update(s);
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return c;
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case AUX_MU_IER_REG:
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/* "DLAB bit set means access baudrate register" is NYI */
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return 0xc0 | s->ier; /* FIFO enables always read 1 */
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case AUX_MU_IIR_REG:
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res = 0xc0; /* FIFO enables */
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/* The spec is unclear on what happens when both tx and rx
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* interrupts are active, besides that this cannot occur. At
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* present, we choose to prioritise the rx interrupt, since
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* the tx fifo is always empty. */
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if (s->read_count != 0) {
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res |= 0x4;
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} else {
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res |= 0x2;
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}
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if (s->iir == 0) {
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res |= 0x1;
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}
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return res;
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case AUX_MU_LCR_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__);
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return 0;
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case AUX_MU_MCR_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__);
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return 0;
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case AUX_MU_LSR_REG:
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res = 0x60; /* tx idle, empty */
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if (s->read_count != 0) {
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res |= 0x1;
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}
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return res;
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case AUX_MU_MSR_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MSR_REG unsupported\n", __func__);
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return 0;
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case AUX_MU_SCRATCH:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__);
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return 0;
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case AUX_MU_CNTL_REG:
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return 0x3; /* tx, rx enabled */
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case AUX_MU_STAT_REG:
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res = 0x30e; /* space in the output buffer, empty tx fifo, idle tx/rx */
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if (s->read_count > 0) {
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res |= 0x1; /* data in input buffer */
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assert(s->read_count < BCM2835_AUX_RX_FIFO_LEN);
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res |= ((uint32_t)s->read_count) << 16; /* rx fifo fill level */
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}
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return res;
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case AUX_MU_BAUD_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__);
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return 0;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
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__func__, offset);
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return 0;
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}
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}
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static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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BCM2835AuxState *s = opaque;
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unsigned char ch;
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switch (offset) {
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case AUX_ENABLES:
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if (value != 1) {
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qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI "
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"or disable UART\n", __func__);
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}
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break;
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case AUX_MU_IO_REG:
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/* "DLAB bit set means access baudrate register" is NYI */
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ch = value;
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if (s->chr) {
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qemu_chr_fe_write(s->chr, &ch, 1);
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}
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break;
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case AUX_MU_IER_REG:
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/* "DLAB bit set means access baudrate register" is NYI */
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s->ier = value & (TX_INT | RX_INT);
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bcm2835_aux_update(s);
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break;
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case AUX_MU_IIR_REG:
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if (value & 0x2) {
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s->read_count = 0;
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}
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break;
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case AUX_MU_LCR_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__);
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break;
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case AUX_MU_MCR_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__);
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break;
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case AUX_MU_SCRATCH:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__);
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break;
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case AUX_MU_CNTL_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_CNTL_REG unsupported\n", __func__);
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break;
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case AUX_MU_BAUD_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
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__func__, offset);
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}
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bcm2835_aux_update(s);
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}
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static int bcm2835_aux_can_receive(void *opaque)
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{
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BCM2835AuxState *s = opaque;
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return s->read_count < BCM2835_AUX_RX_FIFO_LEN;
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}
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static void bcm2835_aux_put_fifo(void *opaque, uint8_t value)
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{
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BCM2835AuxState *s = opaque;
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int slot;
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slot = s->read_pos + s->read_count;
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if (slot >= BCM2835_AUX_RX_FIFO_LEN) {
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slot -= BCM2835_AUX_RX_FIFO_LEN;
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}
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s->read_fifo[slot] = value;
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s->read_count++;
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if (s->read_count == BCM2835_AUX_RX_FIFO_LEN) {
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/* buffer full */
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}
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bcm2835_aux_update(s);
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}
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static void bcm2835_aux_receive(void *opaque, const uint8_t *buf, int size)
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{
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bcm2835_aux_put_fifo(opaque, *buf);
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}
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static const MemoryRegionOps bcm2835_aux_ops = {
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.read = bcm2835_aux_read,
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.write = bcm2835_aux_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static const VMStateDescription vmstate_bcm2835_aux = {
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.name = TYPE_BCM2835_AUX,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8_ARRAY(read_fifo, BCM2835AuxState,
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BCM2835_AUX_RX_FIFO_LEN),
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VMSTATE_UINT8(read_pos, BCM2835AuxState),
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VMSTATE_UINT8(read_count, BCM2835AuxState),
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VMSTATE_UINT8(ier, BCM2835AuxState),
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VMSTATE_UINT8(iir, BCM2835AuxState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void bcm2835_aux_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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BCM2835AuxState *s = BCM2835_AUX(obj);
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memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_aux_ops, s,
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TYPE_BCM2835_AUX, 0x100);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq);
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}
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static void bcm2835_aux_realize(DeviceState *dev, Error **errp)
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{
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BCM2835AuxState *s = BCM2835_AUX(dev);
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if (s->chr) {
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qemu_chr_add_handlers(s->chr, bcm2835_aux_can_receive,
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bcm2835_aux_receive, NULL, s);
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}
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}
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static Property bcm2835_aux_props[] = {
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DEFINE_PROP_CHR("chardev", BCM2835AuxState, chr),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void bcm2835_aux_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = bcm2835_aux_realize;
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dc->vmsd = &vmstate_bcm2835_aux;
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set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
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dc->props = bcm2835_aux_props;
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}
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static const TypeInfo bcm2835_aux_info = {
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.name = TYPE_BCM2835_AUX,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(BCM2835AuxState),
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.instance_init = bcm2835_aux_init,
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.class_init = bcm2835_aux_class_init,
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};
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static void bcm2835_aux_register_types(void)
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{
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type_register_static(&bcm2835_aux_info);
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}
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type_init(bcm2835_aux_register_types)
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@ -14,6 +14,7 @@
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#include "qemu-common.h"
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#include "exec/address-spaces.h"
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#include "hw/sysbus.h"
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#include "hw/char/bcm2835_aux.h"
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#include "hw/intc/bcm2835_ic.h"
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#include "hw/misc/bcm2835_property.h"
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#include "hw/misc/bcm2835_mbox.h"
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@ -33,6 +34,7 @@ typedef struct BCM2835PeripheralState {
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qemu_irq irq, fiq;
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SysBusDevice *uart0;
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BCM2835AuxState aux;
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BCM2835ICState ic;
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BCM2835PropertyState property;
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BCM2835MboxState mboxes;
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@ -0,0 +1,33 @@
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/*
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* Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
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* Written by Andrew Baumann
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*
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* This code is licensed under the GNU GPLv2 and later.
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*/
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#ifndef BCM2835_AUX_H
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#define BCM2835_AUX_H
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#include "hw/sysbus.h"
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#include "sysemu/char.h"
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#define TYPE_BCM2835_AUX "bcm2835-aux"
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#define BCM2835_AUX(obj) OBJECT_CHECK(BCM2835AuxState, (obj), TYPE_BCM2835_AUX)
|
||||
|
||||
#define BCM2835_AUX_RX_FIFO_LEN 8
|
||||
|
||||
typedef struct {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
/*< public >*/
|
||||
|
||||
MemoryRegion iomem;
|
||||
CharDriverState *chr;
|
||||
qemu_irq irq;
|
||||
|
||||
uint8_t read_fifo[BCM2835_AUX_RX_FIFO_LEN];
|
||||
uint8_t read_pos, read_count;
|
||||
uint8_t ier, iir;
|
||||
} BCM2835AuxState;
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue