From 97bf4851fe2542635ebe33bdd1473012a2421b42 Mon Sep 17 00:00:00 2001 From: Blue Swirl Date: Sun, 31 Oct 2010 09:24:14 +0000 Subject: [PATCH] sparc32: convert debug printf statements to tracepoints Replace debug printf statements with tracepoints. Signed-off-by: Blue Swirl --- hw/cs4231.c | 20 +++------ hw/eccmemctl.c | 46 ++++++++----------- hw/lance.c | 14 ++---- hw/slavio_intctl.c | 38 ++++++---------- hw/slavio_misc.c | 51 +++++++++------------ hw/slavio_timer.c | 49 +++++++------------- hw/sparc32_dma.c | 42 ++++++------------ hw/sun4m.c | 18 +++----- hw/sun4m_iommu.c | 33 ++++---------- trace-events | 108 +++++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 213 insertions(+), 206 deletions(-) diff --git a/hw/cs4231.c b/hw/cs4231.c index f7ce0af3f9..2977101e39 100644 --- a/hw/cs4231.c +++ b/hw/cs4231.c @@ -23,9 +23,7 @@ */ #include "sysbus.h" - -/* debug CS4231 */ -//#define DEBUG_CS +#include "trace.h" /* * In addition to Crystal CS4231 there is a DMA controller on Sparc. @@ -46,13 +44,6 @@ typedef struct CSState { #define CS_VER 0xa0 #define CS_CDC_VER 0x8a -#ifdef DEBUG_CS -#define DPRINTF(fmt, ...) \ - do { printf("CS: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF(fmt, ...) -#endif - static void cs_reset(DeviceState *d) { CSState *s = container_of(d, CSState, busdev.qdev); @@ -79,11 +70,11 @@ static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) ret = s->dregs[CS_RAP(s)]; break; } - DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret); + trace_cs4231_mem_readl_dreg(CS_RAP(s), ret); break; default: ret = s->regs[saddr]; - DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret); + trace_cs4231_mem_readl_reg(saddr, ret); break; } return ret; @@ -95,11 +86,10 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) uint32_t saddr; saddr = addr >> 2; - DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val); + trace_cs4231_mem_writel_reg(saddr, s->regs[saddr], val); switch (saddr) { case 1: - DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s), - s->dregs[CS_RAP(s)], val); + trace_cs4231_mem_writel_dreg(CS_RAP(s), s->dregs[CS_RAP(s)], val); switch(CS_RAP(s)) { case 11: case 25: // Read only diff --git a/hw/eccmemctl.c b/hw/eccmemctl.c index 498c61a89c..a8042e94bc 100644 --- a/hw/eccmemctl.c +++ b/hw/eccmemctl.c @@ -23,15 +23,7 @@ */ #include "sysbus.h" - -//#define DEBUG_ECC - -#ifdef DEBUG_ECC -#define DPRINTF(fmt, ...) \ - do { printf("ECC: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF(fmt, ...) -#endif +#include "trace.h" /* There are 3 versions of this chip used in SMP sun4m systems: * MCC (version 0, implementation 0) SS-600MP @@ -148,32 +140,32 @@ static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); else if (s->version == ECC_SMC) s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); - DPRINTF("Write memory enable %08x\n", val); + trace_ecc_mem_writel_mer(val); break; case ECC_MDR: s->regs[ECC_MDR] = val & ECC_MDR_MASK; - DPRINTF("Write memory delay %08x\n", val); + trace_ecc_mem_writel_mdr(val); break; case ECC_MFSR: s->regs[ECC_MFSR] = val; qemu_irq_lower(s->irq); - DPRINTF("Write memory fault status %08x\n", val); + trace_ecc_mem_writel_mfsr(val); break; case ECC_VCR: s->regs[ECC_VCR] = val; - DPRINTF("Write slot configuration %08x\n", val); + trace_ecc_mem_writel_vcr(val); break; case ECC_DR: s->regs[ECC_DR] = val; - DPRINTF("Write diagnostic %08x\n", val); + trace_ecc_mem_writel_dr(val); break; case ECC_ECR0: s->regs[ECC_ECR0] = val; - DPRINTF("Write event count 1 %08x\n", val); + trace_ecc_mem_writel_ecr0(val); break; case ECC_ECR1: s->regs[ECC_ECR0] = val; - DPRINTF("Write event count 2 %08x\n", val); + trace_ecc_mem_writel_ecr1(val); break; } } @@ -186,39 +178,39 @@ static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr) switch (addr >> 2) { case ECC_MER: ret = s->regs[ECC_MER]; - DPRINTF("Read memory enable %08x\n", ret); + trace_ecc_mem_readl_mer(ret); break; case ECC_MDR: ret = s->regs[ECC_MDR]; - DPRINTF("Read memory delay %08x\n", ret); + trace_ecc_mem_readl_mdr(ret); break; case ECC_MFSR: ret = s->regs[ECC_MFSR]; - DPRINTF("Read memory fault status %08x\n", ret); + trace_ecc_mem_readl_mfsr(ret); break; case ECC_VCR: ret = s->regs[ECC_VCR]; - DPRINTF("Read slot configuration %08x\n", ret); + trace_ecc_mem_readl_vcr(ret); break; case ECC_MFAR0: ret = s->regs[ECC_MFAR0]; - DPRINTF("Read memory fault address 0 %08x\n", ret); + trace_ecc_mem_readl_mfar0(ret); break; case ECC_MFAR1: ret = s->regs[ECC_MFAR1]; - DPRINTF("Read memory fault address 1 %08x\n", ret); + trace_ecc_mem_readl_mfar1(ret); break; case ECC_DR: ret = s->regs[ECC_DR]; - DPRINTF("Read diagnostic %08x\n", ret); + trace_ecc_mem_readl_dr(ret); break; case ECC_ECR0: ret = s->regs[ECC_ECR0]; - DPRINTF("Read event count 1 %08x\n", ret); + trace_ecc_mem_readl_ecr0(ret); break; case ECC_ECR1: ret = s->regs[ECC_ECR0]; - DPRINTF("Read event count 2 %08x\n", ret); + trace_ecc_mem_readl_ecr1(ret); break; } return ret; @@ -241,7 +233,7 @@ static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr, { ECCState *s = opaque; - DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val); + trace_ecc_diag_mem_writeb(addr, val); s->diag[addr & ECC_DIAG_MASK] = val; } @@ -250,7 +242,7 @@ static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr) ECCState *s = opaque; uint32_t ret = s->diag[(int)addr]; - DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret); + trace_ecc_diag_mem_readb(addr, ret); return ret; } diff --git a/hw/lance.c b/hw/lance.c index b6b04ddb9c..dc12144ded 100644 --- a/hw/lance.c +++ b/hw/lance.c @@ -40,8 +40,8 @@ #include "qemu-timer.h" #include "qemu_socket.h" #include "sun4m.h" - #include "pcnet.h" +#include "trace.h" typedef struct { SysBusDevice busdev; @@ -59,10 +59,8 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) { SysBusPCNetState *d = opaque; -#ifdef PCNET_DEBUG_IO - printf("lance_mem_writew addr=" TARGET_FMT_plx " val=0x%04x\n", addr, - val & 0xffff); -#endif + + trace_lance_mem_writew(addr, val & 0xffff); pcnet_ioport_writew(&d->state, addr, val & 0xffff); } @@ -72,11 +70,7 @@ static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr) uint32_t val; val = pcnet_ioport_readw(&d->state, addr); -#ifdef PCNET_DEBUG_IO - printf("lance_mem_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr, - val & 0xffff); -#endif - + trace_lance_mem_readw(addr, val & 0xffff); return val & 0xffff; } diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c index 10362a3655..9d5ad86d98 100644 --- a/hw/slavio_intctl.c +++ b/hw/slavio_intctl.c @@ -25,16 +25,9 @@ #include "sun4m.h" #include "monitor.h" #include "sysbus.h" +#include "trace.h" //#define DEBUG_IRQ_COUNT -//#define DEBUG_IRQ - -#ifdef DEBUG_IRQ -#define DPRINTF(fmt, ...) \ - do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF(fmt, ...) -#endif /* * Registers of interrupt controller in sun4m. @@ -97,7 +90,7 @@ static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr) ret = 0; break; } - DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret); + trace_slavio_intctl_mem_readl(s->cpu, addr, ret); return ret; } @@ -109,21 +102,19 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t saddr; saddr = addr >> 2; - DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val); + trace_slavio_intctl_mem_writel(s->cpu, addr, val); switch (saddr) { case 1: // clear pending softints val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN; s->intreg_pending &= ~val; slavio_check_interrupts(s->master, 1); - DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val, - s->intreg_pending); + trace_slavio_intctl_mem_writel_clear(s->cpu, val, s->intreg_pending); break; case 2: // set softint val &= CPU_SOFTIRQ_MASK; s->intreg_pending |= val; slavio_check_interrupts(s->master, 1); - DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val, - s->intreg_pending); + trace_slavio_intctl_mem_writel_set(s->cpu, val, s->intreg_pending); break; default: break; @@ -163,7 +154,7 @@ static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr) ret = 0; break; } - DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret); + trace_slavio_intctlm_mem_readl(addr, ret); return ret; } @@ -175,14 +166,13 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t saddr; saddr = addr >> 2; - DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); + trace_slavio_intctlm_mem_writel(addr, val); switch (saddr) { case 2: // clear (enable) // Force clear unused bits val &= MASTER_IRQ_MASK; s->intregm_disabled &= ~val; - DPRINTF("Enabled master irq mask %x, curmask %x\n", val, - s->intregm_disabled); + trace_slavio_intctlm_mem_writel_enable(val, s->intregm_disabled); slavio_check_interrupts(s, 1); break; case 3: // set (disable; doesn't affect pending) @@ -190,13 +180,12 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, val &= MASTER_IRQ_MASK; s->intregm_disabled |= val; slavio_check_interrupts(s, 1); - DPRINTF("Disabled master irq mask %x, curmask %x\n", val, - s->intregm_disabled); + trace_slavio_intctlm_mem_writel_disable(val, s->intregm_disabled); break; case 4: s->target_cpu = val & (MAX_CPUS - 1); slavio_check_interrupts(s, 1); - DPRINTF("Set master irq cpu %d\n", s->target_cpu); + trace_slavio_intctlm_mem_writel_target(s->target_cpu); break; default: break; @@ -264,7 +253,7 @@ static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs) pending &= ~s->intregm_disabled; - DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled); + trace_slavio_check_interrupts(pending, s->intregm_disabled); for (i = 0; i < MAX_CPUS; i++) { pil_pending = 0; @@ -327,8 +316,7 @@ static void slavio_set_irq(void *opaque, int irq, int level) uint32_t pil = intbit_to_level[irq]; unsigned int i; - DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil, - level); + trace_slavio_set_irq(s->target_cpu, irq, pil, level); if (pil > 0) { if (level) { #ifdef DEBUG_IRQ_COUNT @@ -356,7 +344,7 @@ static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level) { SLAVIO_INTCTLState *s = opaque; - DPRINTF("Set cpu %d local timer level %d\n", cpu, level); + trace_slavio_set_timer_irq_cpu(cpu, level); if (level) { s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN; diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c index 5ae628df8e..1d81a633c7 100644 --- a/hw/slavio_misc.c +++ b/hw/slavio_misc.c @@ -24,9 +24,7 @@ #include "sysemu.h" #include "sysbus.h" - -/* debug misc */ -//#define DEBUG_MISC +#include "trace.h" /* * This is the auxio port, chip control and system control part of @@ -36,13 +34,6 @@ * This also includes the PMC CPU idle controller. */ -#ifdef DEBUG_MISC -#define MISC_DPRINTF(fmt, ...) \ - do { printf("MISC: " fmt , ## __VA_ARGS__); } while (0) -#else -#define MISC_DPRINTF(fmt, ...) -#endif - typedef struct MiscState { SysBusDevice busdev; qemu_irq irq; @@ -79,10 +70,10 @@ static void slavio_misc_update_irq(void *opaque) MiscState *s = opaque; if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) { - MISC_DPRINTF("Raise IRQ\n"); + trace_slavio_misc_update_irq_raise(); qemu_irq_raise(s->irq); } else { - MISC_DPRINTF("Lower IRQ\n"); + trace_slavio_misc_update_irq_lower(); qemu_irq_lower(s->irq); } } @@ -99,7 +90,7 @@ static void slavio_set_power_fail(void *opaque, int irq, int power_failing) { MiscState *s = opaque; - MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config); + trace_slavio_set_power_fail(power_failing, s->config); if (power_failing && (s->config & CFG_PWRINTEN)) { s->aux2 |= AUX2_PWRFAIL; } else { @@ -113,7 +104,7 @@ static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr, { MiscState *s = opaque; - MISC_DPRINTF("Write config %2.2x\n", val & 0xff); + trace_slavio_cfg_mem_writeb(val & 0xff); s->config = val & 0xff; slavio_misc_update_irq(s); } @@ -124,7 +115,7 @@ static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr) uint32_t ret = 0; ret = s->config; - MISC_DPRINTF("Read config %2.2x\n", ret); + trace_slavio_cfg_mem_readb(ret); return ret; } @@ -145,7 +136,7 @@ static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr, { MiscState *s = opaque; - MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); + trace_slavio_diag_mem_writeb(val & 0xff); s->diag = val & 0xff; } @@ -155,7 +146,7 @@ static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr) uint32_t ret = 0; ret = s->diag; - MISC_DPRINTF("Read diag %2.2x\n", ret); + trace_slavio_diag_mem_readb(ret); return ret; } @@ -176,7 +167,7 @@ static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr, { MiscState *s = opaque; - MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); + trace_slavio_mdm_mem_writeb(val & 0xff); s->mctrl = val & 0xff; } @@ -186,7 +177,7 @@ static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr) uint32_t ret = 0; ret = s->mctrl; - MISC_DPRINTF("Read modem control %2.2x\n", ret); + trace_slavio_mdm_mem_readb(ret); return ret; } @@ -207,7 +198,7 @@ static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr, { MiscState *s = opaque; - MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); + trace_slavio_aux1_mem_writeb(val & 0xff); if (val & AUX1_TC) { // Send a pulse to floppy terminal count line if (s->fdc_tc) { @@ -225,8 +216,7 @@ static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr) uint32_t ret = 0; ret = s->aux1; - MISC_DPRINTF("Read aux1 %2.2x\n", ret); - + trace_slavio_aux1_mem_readb(ret); return ret; } @@ -248,7 +238,7 @@ static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr, MiscState *s = opaque; val &= AUX2_PWRINTCLR | AUX2_PWROFF; - MISC_DPRINTF("Write aux2 %2.2x\n", val); + trace_slavio_aux2_mem_writeb(val & 0xff); val |= s->aux2 & AUX2_PWRFAIL; if (val & AUX2_PWRINTCLR) // Clear Power Fail int val &= AUX2_PWROFF; @@ -264,8 +254,7 @@ static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr) uint32_t ret = 0; ret = s->aux2; - MISC_DPRINTF("Read aux2 %2.2x\n", ret); - + trace_slavio_aux2_mem_readb(ret); return ret; } @@ -285,7 +274,7 @@ static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) { APCState *s = opaque; - MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); + trace_apc_mem_writeb(val & 0xff); qemu_irq_raise(s->cpu_halt); } @@ -293,7 +282,7 @@ static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr) { uint32_t ret = 0; - MISC_DPRINTF("Read power management %2.2x\n", ret); + trace_apc_mem_readb(ret); return ret; } @@ -321,7 +310,7 @@ static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr) default: break; } - MISC_DPRINTF("Read system control %08x\n", ret); + trace_slavio_sysctrl_mem_readl(ret); return ret; } @@ -330,7 +319,7 @@ static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr, { MiscState *s = opaque; - MISC_DPRINTF("Write system control %08x\n", val); + trace_slavio_sysctrl_mem_writel(val); switch (addr) { case 0: if (val & SYS_RESET) { @@ -367,7 +356,7 @@ static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr) default: break; } - MISC_DPRINTF("Read diagnostic LED %04x\n", ret); + trace_slavio_led_mem_readw(ret); return ret; } @@ -376,7 +365,7 @@ static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr, { MiscState *s = opaque; - MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff); + trace_slavio_led_mem_readw(val & 0xffff); switch (addr) { case 0: s->leds = val; diff --git a/hw/slavio_timer.c b/hw/slavio_timer.c index c125de4b62..13f1e62ad8 100644 --- a/hw/slavio_timer.c +++ b/hw/slavio_timer.c @@ -25,15 +25,7 @@ #include "sun4m.h" #include "qemu-timer.h" #include "sysbus.h" - -//#define DEBUG_TIMER - -#ifdef DEBUG_TIMER -#define DPRINTF(fmt, ...) \ - do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF(fmt, ...) do {} while (0) -#endif +#include "trace.h" /* * Registers of hardware timer in sun4m. @@ -112,8 +104,7 @@ static void slavio_timer_get_out(CPUTimerState *t) } count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); - DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", t->limit, t->counthigh, - t->count); + trace_slavio_timer_get_out(t->limit, t->counthigh, t->count); t->count = count & TIMER_COUNT_MASK32; t->counthigh = count >> 32; } @@ -126,7 +117,7 @@ static void slavio_timer_irq(void *opaque) CPUTimerState *t = &s->cputimer[tc->timer_index]; slavio_timer_get_out(t); - DPRINTF("callback: count %x%08x\n", t->counthigh, t->count); + trace_slavio_timer_irq(t->counthigh, t->count); /* if limit is 0 (free-run), there will be no match */ if (t->limit != 0) { t->reached = TIMER_REACHED; @@ -188,12 +179,11 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) ret = s->cputimer_mode; break; default: - DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr); + trace_slavio_timer_mem_readl_invalid(addr); ret = 0; break; } - DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret); - + trace_slavio_timer_mem_readl(addr, ret); return ret; } @@ -206,7 +196,7 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, unsigned int timer_index = tc->timer_index; CPUTimerState *t = &s->cputimer[timer_index]; - DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val); + trace_slavio_timer_mem_writel(addr, val); saddr = addr >> 2; switch (saddr) { case TIMER_LIMIT: @@ -218,8 +208,7 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, t->counthigh = val & (TIMER_MAX_COUNT64 >> 32); t->reached = 0; count = ((uint64_t)t->counthigh << 32) | t->count; - DPRINTF("processor %d user timer set to %016" PRIx64 "\n", - timer_index, count); + trace_slavio_timer_mem_writel_limit(timer_index, count); ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); } else { // set limit, reset counter @@ -244,11 +233,11 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, t->count = val & TIMER_MAX_COUNT64; t->reached = 0; count = ((uint64_t)t->counthigh) << 32 | t->count; - DPRINTF("processor %d user timer set to %016" PRIx64 "\n", - timer_index, count); + trace_slavio_timer_mem_writel_limit(timer_index, count); ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); - } else - DPRINTF("not user timer\n"); + } else { + trace_slavio_timer_mem_writel_counter_invalid(); + } break; case TIMER_COUNTER_NORST: // set limit without resetting counter @@ -263,13 +252,11 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, if (slavio_timer_is_user(tc)) { // start/stop user counter if ((val & 1) && !t->running) { - DPRINTF("processor %d user timer started\n", - timer_index); + trace_slavio_timer_mem_writel_status_start(timer_index); ptimer_run(t->timer, 0); t->running = 1; } else if (!(val & 1) && t->running) { - DPRINTF("processor %d user timer stopped\n", - timer_index); + trace_slavio_timer_mem_writel_status_stop(timer_index); ptimer_stop(t->timer); t->running = 0; } @@ -298,8 +285,7 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, // set this processors user timer bit in config // register s->cputimer_mode |= processor; - DPRINTF("processor %d changed from counter to user " - "timer\n", timer_index); + trace_slavio_timer_mem_writel_mode_user(timer_index); } else { // user timer -> counter // stop the user timer if it is running if (curr_timer->running) { @@ -311,17 +297,16 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, // clear this processors user timer bit in config // register s->cputimer_mode &= ~processor; - DPRINTF("processor %d changed from user timer to " - "counter\n", timer_index); + trace_slavio_timer_mem_writel_mode_counter(timer_index); } } } } else { - DPRINTF("not system timer\n"); + trace_slavio_timer_mem_writel_mode_invalid(); } break; default: - DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr); + trace_slavio_timer_mem_writel_invalid(addr); break; } } diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c index 984ffc3e53..0904188c95 100644 --- a/hw/sparc32_dma.c +++ b/hw/sparc32_dma.c @@ -29,9 +29,7 @@ #include "sparc32_dma.h" #include "sun4m.h" #include "sysbus.h" - -/* debug DMA */ -//#define DEBUG_DMA +#include "trace.h" /* * This is the DMA controller part of chip STP2000 (Master I/O), also @@ -41,13 +39,6 @@ * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt */ -#ifdef DEBUG_DMA -#define DPRINTF(fmt, ...) \ - do { printf("DMA: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF(fmt, ...) -#endif - #define DMA_REGS 4 #define DMA_SIZE (4 * sizeof(uint32_t)) /* We need the mask, because one instance of the device is not page @@ -88,9 +79,8 @@ void ledma_memory_read(void *opaque, target_phys_addr_t addr, DMAState *s = opaque; int i; - DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n", - s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); addr |= s->dmaregs[3]; + trace_ledma_memory_read(addr); if (do_bswap) { sparc_iommu_memory_read(s->iommu, addr, buf, len); } else { @@ -110,9 +100,8 @@ void ledma_memory_write(void *opaque, target_phys_addr_t addr, int l, i; uint16_t tmp_buf[32]; - DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n", - s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); addr |= s->dmaregs[3]; + trace_ledma_memory_write(addr); if (do_bswap) { sparc_iommu_memory_write(s->iommu, addr, buf, len); } else { @@ -139,14 +128,14 @@ static void dma_set_irq(void *opaque, int irq, int level) if (level) { s->dmaregs[0] |= DMA_INTR; if (s->dmaregs[0] & DMA_INTREN) { - DPRINTF("Raise IRQ\n"); + trace_sparc32_dma_set_irq_raise(); qemu_irq_raise(s->irq); } } else { if (s->dmaregs[0] & DMA_INTR) { s->dmaregs[0] &= ~DMA_INTR; if (s->dmaregs[0] & DMA_INTREN) { - DPRINTF("Lower IRQ\n"); + trace_sparc32_dma_set_irq_lower(); qemu_irq_lower(s->irq); } } @@ -157,8 +146,7 @@ void espdma_memory_read(void *opaque, uint8_t *buf, int len) { DMAState *s = opaque; - DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n", - s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); + trace_espdma_memory_read(s->dmaregs[1]); sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len); s->dmaregs[1] += len; } @@ -167,8 +155,7 @@ void espdma_memory_write(void *opaque, uint8_t *buf, int len) { DMAState *s = opaque; - DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n", - s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); + trace_espdma_memory_write(s->dmaregs[1]); sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len); s->dmaregs[1] += len; } @@ -179,9 +166,7 @@ static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr) uint32_t saddr; saddr = (addr & DMA_MASK) >> 2; - DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr, - s->dmaregs[saddr]); - + trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]); return s->dmaregs[saddr]; } @@ -191,18 +176,17 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) uint32_t saddr; saddr = (addr & DMA_MASK) >> 2; - DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr, - s->dmaregs[saddr], val); + trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val); switch (saddr) { case 0: if (val & DMA_INTREN) { if (s->dmaregs[0] & DMA_INTR) { - DPRINTF("Raise IRQ\n"); + trace_sparc32_dma_set_irq_raise(); qemu_irq_raise(s->irq); } } else { if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) { - DPRINTF("Lower IRQ\n"); + trace_sparc32_dma_set_irq_lower(); qemu_irq_lower(s->irq); } } @@ -215,10 +199,10 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) val = DMA_DRAIN_FIFO; if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) { - DPRINTF("Raise DMA enable\n"); + trace_sparc32_dma_enable_raise(); qemu_irq_raise(s->gpio[GPIO_DMA]); } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) { - DPRINTF("Lower DMA enable\n"); + trace_sparc32_dma_enable_lower(); qemu_irq_lower(s->gpio[GPIO_DMA]); } diff --git a/hw/sun4m.c b/hw/sun4m.c index 0392109230..4795b3f45e 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -41,8 +41,7 @@ #include "loader.h" #include "elf.h" #include "blockdev.h" - -//#define DEBUG_IRQ +#include "trace.h" /* * Sun4m architecture was used in the following machines: @@ -72,13 +71,6 @@ * See for example: http://www.sunhelp.org/faq/sunref1.html */ -#ifdef DEBUG_IRQ -#define DPRINTF(fmt, ...) \ - do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF(fmt, ...) -#endif - #define KERNEL_LOAD_ADDR 0x00004000 #define CMDLINE_ADDR 0x007ff000 #define INITRD_LOAD_ADDR 0x00800000 @@ -248,14 +240,14 @@ void cpu_check_irqs(CPUState *env) env->interrupt_index = TT_EXTINT | i; if (old_interrupt != env->interrupt_index) { - DPRINTF("Set CPU IRQ %d\n", i); + trace_sun4m_cpu_interrupt(i); cpu_interrupt(env, CPU_INTERRUPT_HARD); } break; } } } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { - DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); + trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); env->interrupt_index = 0; cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); } @@ -266,12 +258,12 @@ static void cpu_set_irq(void *opaque, int irq, int level) CPUState *env = opaque; if (level) { - DPRINTF("Raise CPU IRQ %d\n", irq); + trace_sun4m_cpu_set_irq_raise(irq); env->halted = 0; env->pil_in |= 1 << irq; cpu_check_irqs(env); } else { - DPRINTF("Lower CPU IRQ %d\n", irq); + trace_sun4m_cpu_set_irq_lower(irq); env->pil_in &= ~(1 << irq); cpu_check_irqs(env); } diff --git a/hw/sun4m_iommu.c b/hw/sun4m_iommu.c index 1dbe077466..720ee3f0bd 100644 --- a/hw/sun4m_iommu.c +++ b/hw/sun4m_iommu.c @@ -24,16 +24,7 @@ #include "sun4m.h" #include "sysbus.h" - -/* debug iommu */ -//#define DEBUG_IOMMU - -#ifdef DEBUG_IOMMU -#define DPRINTF(fmt, ...) \ - do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF(fmt, ...) -#endif +#include "trace.h" /* * I/O MMU used by Sun4m systems @@ -160,7 +151,7 @@ static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr) qemu_irq_lower(s->irq); break; } - DPRINTF("read reg[%d] = %x\n", (int)saddr, ret); + trace_sun4m_iommu_mem_readl(saddr, ret); return ret; } @@ -171,7 +162,7 @@ static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, target_phys_addr_t saddr; saddr = addr >> 2; - DPRINTF("write reg[%d] = %x\n", (int)saddr, val); + trace_sun4m_iommu_mem_writel(saddr, val); switch (saddr) { case IOMMU_CTRL: switch (val & IOMMU_CTRL_RNGE) { @@ -201,18 +192,18 @@ static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, s->iostart = 0xffffffff80000000ULL; break; } - DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart); + trace_sun4m_iommu_mem_writel_ctrl(s->iostart); s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version); break; case IOMMU_BASE: s->regs[saddr] = val & IOMMU_BASE_MASK; break; case IOMMU_TLBFLUSH: - DPRINTF("tlb flush %x\n", val); + trace_sun4m_iommu_mem_writel_tlbflush(val); s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; break; case IOMMU_PGFLUSH: - DPRINTF("page flush %x\n", val); + trace_sun4m_iommu_mem_writel_pgflush(val); s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; break; case IOMMU_AFAR: @@ -262,18 +253,14 @@ static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr) { uint32_t ret; target_phys_addr_t iopte; -#ifdef DEBUG_IOMMU target_phys_addr_t pa = addr; -#endif iopte = s->regs[IOMMU_BASE] << 4; addr &= ~s->iostart; iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3; cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4); tswap32s(&ret); - DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx - ", *pte = %x\n", pa, iopte, ret); - + trace_sun4m_iommu_page_get_flags(pa, iopte, ret); return ret; } @@ -283,16 +270,14 @@ static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr, target_phys_addr_t pa; pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK); - DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx - " (iopte = %x)\n", addr, pa, pte); - + trace_sun4m_iommu_translate_pa(addr, pa, pte); return pa; } static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, int is_write) { - DPRINTF("bad addr " TARGET_FMT_plx "\n", addr); + trace_sun4m_iommu_bad_addr(addr); s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV | IOMMU_AFSR_FAV; if (!is_write) diff --git a/trace-events b/trace-events index ed2055e425..947f8b08cb 100644 --- a/trace-events +++ b/trace-events @@ -81,3 +81,111 @@ disable apic_mem_writel(uint64_t addr, uint32_t val) "%"PRIx64" = %08x" disable apic_reset_irq_delivered(int apic_irq_delivered) "old coalescing %d" disable apic_get_irq_delivered(int apic_irq_delivered) "returning coalescing %d" disable apic_set_irq(int apic_irq_delivered) "coalescing %d" + +# hw/cs4231.c +disable cs4231_mem_readl_dreg(uint32_t reg, uint32_t ret) "read dreg %d: 0x%02x" +disable cs4231_mem_readl_reg(uint32_t reg, uint32_t ret) "read reg %d: 0x%08x" +disable cs4231_mem_writel_reg(uint32_t reg, uint32_t old, uint32_t val) "write reg %d: 0x%08x -> 0x%08x" +disable cs4231_mem_writel_dreg(uint32_t reg, uint32_t old, uint32_t val) "write dreg %d: 0x%02x -> 0x%02x" + +# hw/eccmemctl.c +disable ecc_mem_writel_mer(uint32_t val) "Write memory enable %08x" +disable ecc_mem_writel_mdr(uint32_t val) "Write memory delay %08x" +disable ecc_mem_writel_mfsr(uint32_t val) "Write memory fault status %08x" +disable ecc_mem_writel_vcr(uint32_t val) "Write slot configuration %08x" +disable ecc_mem_writel_dr(uint32_t val) "Write diagnostic %08x" +disable ecc_mem_writel_ecr0(uint32_t val) "Write event count 1 %08x" +disable ecc_mem_writel_ecr1(uint32_t val) "Write event count 2 %08x" +disable ecc_mem_readl_mer(uint32_t ret) "Read memory enable %08x" +disable ecc_mem_readl_mdr(uint32_t ret) "Read memory delay %08x" +disable ecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status %08x" +disable ecc_mem_readl_vcr(uint32_t ret) "Read slot configuration %08x" +disable ecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 %08x" +disable ecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 %08x" +disable ecc_mem_readl_dr(uint32_t ret) "Read diagnostic %08x" +disable ecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 %08x" +disable ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 %08x" +disable ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = %02x" +disable ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= %02x" + +# hw/lance.c +disable lance_mem_readw(uint64_t addr, uint32_t ret) "addr=%"PRIx64"val=0x%04x" +disable lance_mem_writew(uint64_t addr, uint32_t val) "addr=%"PRIx64"val=0x%04x" + +# hw/slavio_intctl.c +disable slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = %x" +disable slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" = %x" +disable slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Cleared cpu %d irq mask %x, curmask %x" +disable slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Set cpu %d irq mask %x, curmask %x" +disable slavio_intctlm_mem_readl(uint64_t addr, uint32_t ret) "read system reg 0x%"PRIx64" = %x" +disable slavio_intctlm_mem_writel(uint64_t addr, uint32_t val) "write system reg 0x%"PRIx64" = %x" +disable slavio_intctlm_mem_writel_enable(uint32_t val, uint32_t intregm_disabled) "Enabled master irq mask %x, curmask %x" +disable slavio_intctlm_mem_writel_disable(uint32_t val, uint32_t intregm_disabled) "Disabled master irq mask %x, curmask %x" +disable slavio_intctlm_mem_writel_target(uint32_t cpu) "Set master irq cpu %d" +disable slavio_check_interrupts(uint32_t pending, uint32_t intregm_disabled) "pending %x disabled %x" +disable slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d level %d" +disable slavio_set_timer_irq_cpu(int cpu, int level) "Set cpu %d local timer level %d" + +# hw/slavio_misc.c +disable slavio_misc_update_irq_raise(void) "Raise IRQ" +disable slavio_misc_update_irq_lower(void) "Lower IRQ" +disable slavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d" +disable slavio_cfg_mem_writeb(uint32_t val) "Write config %02x" +disable slavio_cfg_mem_readb(uint32_t ret) "Read config %02x" +disable slavio_diag_mem_writeb(uint32_t val) "Write diag %02x" +disable slavio_diag_mem_readb(uint32_t ret) "Read diag %02x" +disable slavio_mdm_mem_writeb(uint32_t val) "Write modem control %02x" +disable slavio_mdm_mem_readb(uint32_t ret) "Read modem control %02x" +disable slavio_aux1_mem_writeb(uint32_t val) "Write aux1 %02x" +disable slavio_aux1_mem_readb(uint32_t ret) "Read aux1 %02x" +disable slavio_aux2_mem_writeb(uint32_t val) "Write aux2 %02x" +disable slavio_aux2_mem_readb(uint32_t ret) "Read aux2 %02x" +disable apc_mem_writeb(uint32_t val) "Write power management %02x" +disable apc_mem_readb(uint32_t ret) "Read power management %02x" +disable slavio_sysctrl_mem_writel(uint32_t val) "Write system control %08x" +disable slavio_sysctrl_mem_readl(uint32_t ret) "Read system control %08x" +disable slavio_led_mem_writew(uint32_t val) "Write diagnostic LED %04x" +disable slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED %04x" + +# hw/slavio_timer.c +disable slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit %"PRIx64" count %x%08x" +disable slavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count %x%08x" +disable slavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address %"PRIx64"" +disable slavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read %"PRIx64" = %08x" +disable slavio_timer_mem_writel(uint64_t addr, uint32_t val) "write %"PRIx64" = %08x" +disable slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to %016"PRIx64"" +disable slavio_timer_mem_writel_counter_invalid(void) "not user timer" +disable slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started" +disable slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped" +disable slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer" +disable slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter" +disable slavio_timer_mem_writel_mode_invalid(void) "not system timer" +disable slavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address %"PRIx64"" + +# hw/sparc32_dma.c +disable ledma_memory_read(uint64_t addr) "DMA read addr 0x%"PRIx64"" +disable ledma_memory_write(uint64_t addr) "DMA write addr 0x%"PRIx64"" +disable sparc32_dma_set_irq_raise(void) "Raise IRQ" +disable sparc32_dma_set_irq_lower(void) "Lower IRQ" +disable espdma_memory_read(uint32_t addr) "DMA read addr 0x%08x" +disable espdma_memory_write(uint32_t addr) "DMA write addr 0x%08x" +disable sparc32_dma_mem_readl(uint64_t addr, uint32_t ret) "read dmareg %"PRIx64": 0x%08x" +disable sparc32_dma_mem_writel(uint64_t addr, uint32_t old, uint32_t val) "write dmareg %"PRIx64": 0x%08x -> 0x%08x" +disable sparc32_dma_enable_raise(void) "Raise DMA enable" +disable sparc32_dma_enable_lower(void) "Lower DMA enable" + +# hw/sun4m.c +disable sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d" +disable sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d" +disable sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d" +disable sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d" + +# hw/sun4m_iommu.c +disable sun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[%"PRIx64"] = %x" +disable sun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[%"PRIx64"] = %x" +disable sun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart = %"PRIx64"" +disable sun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush %x" +disable sun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush %x" +disable sun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get flags addr %"PRIx64" => pte %"PRIx64", *pte = %x" +disable sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva %"PRIx64" => pa %"PRIx64" iopte = %x" +disable sun4m_iommu_bad_addr(uint64_t addr) "bad addr %"PRIx64""