tcg/aarch64: Split up is_fimm
There are several sub-classes of vector immediate, and only MOVI can use them all. This will enable usage of MVNI and ORRI, which use progressively fewer sub-classes. This patch adds no new functionality, merely splits the function and moves part of the logic into tcg_out_dupi_vec. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson
parent
a9e434a5dc
commit
984fdcee34
@ -190,103 +190,86 @@ static inline bool is_limm(uint64_t val)
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return (val & (val - 1)) == 0;
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}
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/* Match a constant that is valid for vectors. */
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static bool is_fimm(uint64_t v64, int *op, int *cmode, int *imm8)
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/* Return true if v16 is a valid 16-bit shifted immediate. */
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static bool is_shimm16(uint16_t v16, int *cmode, int *imm8)
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{
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int i;
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*op = 0;
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/* Match replication across 8 bits. */
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if (v64 == dup_const(MO_8, v64)) {
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*cmode = 0xe;
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*imm8 = v64 & 0xff;
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if (v16 == (v16 & 0xff)) {
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*cmode = 0x8;
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*imm8 = v16 & 0xff;
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return true;
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} else if (v16 == (v16 & 0xff00)) {
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*cmode = 0xa;
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*imm8 = v16 >> 8;
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return true;
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}
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/* Match replication across 16 bits. */
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if (v64 == dup_const(MO_16, v64)) {
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uint16_t v16 = v64;
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return false;
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}
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if (v16 == (v16 & 0xff)) {
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*cmode = 0x8;
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*imm8 = v16 & 0xff;
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return true;
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} else if (v16 == (v16 & 0xff00)) {
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*cmode = 0xa;
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*imm8 = v16 >> 8;
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return true;
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}
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/* Return true if v32 is a valid 32-bit shifted immediate. */
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static bool is_shimm32(uint32_t v32, int *cmode, int *imm8)
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{
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if (v32 == (v32 & 0xff)) {
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*cmode = 0x0;
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*imm8 = v32 & 0xff;
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return true;
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} else if (v32 == (v32 & 0xff00)) {
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*cmode = 0x2;
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*imm8 = (v32 >> 8) & 0xff;
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return true;
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} else if (v32 == (v32 & 0xff0000)) {
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*cmode = 0x4;
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*imm8 = (v32 >> 16) & 0xff;
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return true;
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} else if (v32 == (v32 & 0xff000000)) {
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*cmode = 0x6;
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*imm8 = v32 >> 24;
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return true;
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}
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/* Match replication across 32 bits. */
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if (v64 == dup_const(MO_32, v64)) {
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uint32_t v32 = v64;
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return false;
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}
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if (v32 == (v32 & 0xff)) {
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*cmode = 0x0;
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*imm8 = v32 & 0xff;
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return true;
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} else if (v32 == (v32 & 0xff00)) {
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*cmode = 0x2;
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*imm8 = (v32 >> 8) & 0xff;
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return true;
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} else if (v32 == (v32 & 0xff0000)) {
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*cmode = 0x4;
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*imm8 = (v32 >> 16) & 0xff;
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return true;
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} else if (v32 == (v32 & 0xff000000)) {
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*cmode = 0x6;
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*imm8 = v32 >> 24;
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return true;
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} else if ((v32 & 0xffff00ff) == 0xff) {
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*cmode = 0xc;
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*imm8 = (v32 >> 8) & 0xff;
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return true;
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} else if ((v32 & 0xff00ffff) == 0xffff) {
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*cmode = 0xd;
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*imm8 = (v32 >> 16) & 0xff;
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return true;
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}
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/* Match forms of a float32. */
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if (extract32(v32, 0, 19) == 0
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&& (extract32(v32, 25, 6) == 0x20
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|| extract32(v32, 25, 6) == 0x1f)) {
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*cmode = 0xf;
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*imm8 = (extract32(v32, 31, 1) << 7)
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| (extract32(v32, 25, 1) << 6)
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| extract32(v32, 19, 6);
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return true;
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}
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/* Return true if v32 is a valid 32-bit shifting ones immediate. */
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static bool is_soimm32(uint32_t v32, int *cmode, int *imm8)
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{
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if ((v32 & 0xffff00ff) == 0xff) {
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*cmode = 0xc;
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*imm8 = (v32 >> 8) & 0xff;
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return true;
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} else if ((v32 & 0xff00ffff) == 0xffff) {
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*cmode = 0xd;
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*imm8 = (v32 >> 16) & 0xff;
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return true;
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}
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/* Match forms of a float64. */
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return false;
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}
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/* Return true if v32 is a valid float32 immediate. */
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static bool is_fimm32(uint32_t v32, int *cmode, int *imm8)
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{
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if (extract32(v32, 0, 19) == 0
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&& (extract32(v32, 25, 6) == 0x20
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|| extract32(v32, 25, 6) == 0x1f)) {
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*cmode = 0xf;
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*imm8 = (extract32(v32, 31, 1) << 7)
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| (extract32(v32, 25, 1) << 6)
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| extract32(v32, 19, 6);
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return true;
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}
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return false;
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}
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/* Return true if v64 is a valid float64 immediate. */
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static bool is_fimm64(uint64_t v64, int *cmode, int *imm8)
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{
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if (extract64(v64, 0, 48) == 0
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&& (extract64(v64, 54, 9) == 0x100
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|| extract64(v64, 54, 9) == 0x0ff)) {
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*cmode = 0xf;
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*op = 1;
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*imm8 = (extract64(v64, 63, 1) << 7)
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| (extract64(v64, 54, 1) << 6)
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| extract64(v64, 48, 6);
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return true;
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}
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/* Match bytes of 0x00 and 0xff. */
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for (i = 0; i < 64; i += 8) {
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uint64_t byte = extract64(v64, i, 8);
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if (byte != 0 && byte != 0xff) {
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break;
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}
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}
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if (i == 64) {
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*cmode = 0xe;
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*op = 1;
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*imm8 = (extract64(v64, 0, 1) << 0)
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| (extract64(v64, 8, 1) << 1)
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| (extract64(v64, 16, 1) << 2)
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| (extract64(v64, 24, 1) << 3)
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| (extract64(v64, 32, 1) << 4)
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| (extract64(v64, 40, 1) << 5)
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| (extract64(v64, 48, 1) << 6)
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| (extract64(v64, 56, 1) << 7);
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return true;
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}
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return false;
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}
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@ -817,11 +800,63 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
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static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
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TCGReg rd, tcg_target_long v64)
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{
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int op, cmode, imm8;
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bool q = type == TCG_TYPE_V128;
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int cmode, imm8, i;
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if (is_fimm(v64, &op, &cmode, &imm8)) {
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tcg_out_insn(s, 3606, MOVI, type == TCG_TYPE_V128, rd, op, cmode, imm8);
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} else if (type == TCG_TYPE_V128) {
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/* Test all bytes equal first. */
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if (v64 == dup_const(MO_8, v64)) {
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imm8 = (uint8_t)v64;
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tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8);
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return;
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}
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/*
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* Test all bytes 0x00 or 0xff second. This can match cases that
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* might otherwise take 2 or 3 insns for MO_16 or MO_32 below.
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*/
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for (i = imm8 = 0; i < 8; i++) {
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uint8_t byte = v64 >> (i * 8);
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if (byte == 0xff) {
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imm8 |= 1 << i;
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} else if (byte != 0) {
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goto fail_bytes;
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}
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}
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tcg_out_insn(s, 3606, MOVI, q, rd, 1, 0xe, imm8);
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return;
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fail_bytes:
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/*
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* Tests for various replications. For each element width, if we
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* cannot find an expansion there's no point checking a larger
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* width because we already know by replication it cannot match.
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*/
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if (v64 == dup_const(MO_16, v64)) {
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uint16_t v16 = v64;
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if (is_shimm16(v16, &cmode, &imm8)) {
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tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);
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return;
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}
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} else if (v64 == dup_const(MO_32, v64)) {
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uint32_t v32 = v64;
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if (is_shimm32(v32, &cmode, &imm8) ||
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is_soimm32(v32, &cmode, &imm8) ||
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is_fimm32(v32, &cmode, &imm8)) {
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tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);
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return;
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}
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} else if (is_fimm64(v64, &cmode, &imm8)) {
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tcg_out_insn(s, 3606, MOVI, q, rd, 1, cmode, imm8);
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return;
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}
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/*
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* As a last resort, load from the constant pool. Sadly there
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* is no LD1R (literal), so store the full 16-byte vector.
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*/
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if (type == TCG_TYPE_V128) {
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new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, v64, v64);
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tcg_out_insn(s, 3305, LDR_v128, 0, rd);
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} else {
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