disas/riscv.c: Fix lines with over 80 characters
Fix lines with over 80 characters. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li
Alistair Francis
parent
8deb4756a9
commit
98624d1373
201
disas/riscv.c
201
disas/riscv.c
@ -1110,8 +1110,10 @@ static const char rv_vreg_name_sym[32][4] = {
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/* pseudo-instruction constraints */
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static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end };
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static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, rvc_end };
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static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero, rvc_end };
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static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero,
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rvc_end };
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static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0,
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rvc_imm_eq_zero, rvc_end };
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static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
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static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
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static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
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@ -1141,18 +1143,28 @@ static const rvc_constraint rvcc_bleu[] = { rvc_end };
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static const rvc_constraint rvcc_bgt[] = { rvc_end };
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static const rvc_constraint rvcc_bgtu[] = { rvc_end };
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static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
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static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, rvc_end };
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static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end };
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static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, rvc_end };
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static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, rvc_end };
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static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end };
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static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end };
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static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end };
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static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
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rvc_end };
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static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
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rvc_end };
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static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00,
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rvc_end };
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static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01,
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rvc_end };
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static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0,
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rvc_csr_eq_0xc02, rvc_end };
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static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0,
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rvc_csr_eq_0xc80, rvc_end };
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static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81,
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rvc_end };
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static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
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rvc_csr_eq_0xc82, rvc_end };
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static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end };
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static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end };
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static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end };
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static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003,
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rvc_end };
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static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002,
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rvc_end };
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static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001,
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rvc_end };
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static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end };
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static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end };
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static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end };
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@ -1554,17 +1566,23 @@ const rv_opcode_data opcode_data[] = {
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{ "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
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{ "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
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rv_op_addi, rv_op_addi, rvcd_imm_nz },
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{ "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 },
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{ "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
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{ "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
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rv_op_fld, 0 },
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{ "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw,
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rv_op_lw },
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{ "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
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{ "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, 0 },
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{ "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
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{ "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
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rv_op_fsd, 0 },
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{ "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw,
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rv_op_sw },
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{ "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
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{ "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
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{ "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi,
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rv_op_addi },
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{ "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
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rv_op_addi, rvcd_imm_nz },
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{ "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
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{ "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
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{ "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
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rv_op_addi },
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{ "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
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rv_op_addi, rv_op_addi, rvcd_imm_nz },
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{ "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui,
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@ -1575,37 +1593,63 @@ const rv_opcode_data opcode_data[] = {
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rv_op_srai, rv_op_srai, rvcd_imm_nz },
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{ "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
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rv_op_andi, rv_op_andi },
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{ "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub },
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{ "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor },
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{ "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or },
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{ "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, rv_op_and },
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{ "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, rv_op_subw },
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{ "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, rv_op_addw },
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{ "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal },
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{ "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq },
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{ "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne },
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{ "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub,
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rv_op_sub },
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{ "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor,
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rv_op_xor },
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{ "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or,
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rv_op_or },
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{ "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and,
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rv_op_and },
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{ "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw,
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rv_op_subw },
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{ "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw,
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rv_op_addw },
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{ "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal,
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rv_op_jal },
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{ "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq,
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rv_op_beq },
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{ "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne,
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rv_op_bne },
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{ "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli,
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rv_op_slli, rv_op_slli, rvcd_imm_nz },
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{ "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld },
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{ "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
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{ "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
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{ "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
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{ "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
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{ "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, rv_op_ebreak, rv_op_ebreak },
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{ "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
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{ "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, rv_op_add },
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{ "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, rv_op_fsd },
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{ "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
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{ "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
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{ "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
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{ "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
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{ "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, rv_op_addiw },
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{ "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
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{ "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
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{ "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
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rv_op_fld, rv_op_fld },
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{ "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
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rv_op_lw, rv_op_lw },
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{ "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0,
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0 },
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{ "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
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rv_op_jalr, rv_op_jalr },
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{ "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi,
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rv_op_addi },
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{ "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak,
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rv_op_ebreak, rv_op_ebreak },
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{ "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
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rv_op_jalr, rv_op_jalr },
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{ "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add,
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rv_op_add },
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{ "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
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rv_op_fsd, rv_op_fsd },
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{ "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw,
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rv_op_sw, rv_op_sw },
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{ "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0,
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0 },
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{ "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
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rv_op_ld },
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{ "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
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rv_op_sd },
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{ "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw,
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rv_op_addiw },
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{ "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
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rv_op_ld },
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{ "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
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rv_op_sd },
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{ "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
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{ "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
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{ "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
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{ "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
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{ "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0,
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rv_op_sq },
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{ "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
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{ "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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@ -2844,7 +2888,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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}
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break;
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case 11:
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switch (((inst >> 24) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
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switch (((inst >> 24) & 0b11111000) |
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((inst >> 12) & 0b00000111)) {
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case 2: op = rv_op_amoadd_w; break;
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case 3: op = rv_op_amoadd_d; break;
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case 4: op = rv_op_amoadd_q; break;
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@ -2893,7 +2938,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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}
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break;
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case 12:
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switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
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switch (((inst >> 22) & 0b1111111000) |
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((inst >> 12) & 0b0000000111)) {
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case 0: op = rv_op_add; break;
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case 1: op = rv_op_sll; break;
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case 2: op = rv_op_slt; break;
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@ -2966,7 +3012,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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break;
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case 13: op = rv_op_lui; break;
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case 14:
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switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
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switch (((inst >> 22) & 0b1111111000) |
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((inst >> 12) & 0b0000000111)) {
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case 0: op = rv_op_addw; break;
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case 1: op = rv_op_sllw; break;
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case 5: op = rv_op_srlw; break;
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@ -3175,35 +3222,41 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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}
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break;
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case 112:
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switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
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switch (((inst >> 17) & 0b11111000) |
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((inst >> 12) & 0b00000111)) {
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case 0: op = rv_op_fmv_x_s; break;
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case 1: op = rv_op_fclass_s; break;
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}
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break;
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case 113:
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switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
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switch (((inst >> 17) & 0b11111000) |
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((inst >> 12) & 0b00000111)) {
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case 0: op = rv_op_fmv_x_d; break;
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case 1: op = rv_op_fclass_d; break;
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}
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break;
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case 115:
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switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
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switch (((inst >> 17) & 0b11111000) |
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((inst >> 12) & 0b00000111)) {
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case 0: op = rv_op_fmv_x_q; break;
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case 1: op = rv_op_fclass_q; break;
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}
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break;
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case 120:
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switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
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switch (((inst >> 17) & 0b11111000) |
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((inst >> 12) & 0b00000111)) {
|
||||
case 0: op = rv_op_fmv_s_x; break;
|
||||
}
|
||||
break;
|
||||
case 121:
|
||||
switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
|
||||
switch (((inst >> 17) & 0b11111000) |
|
||||
((inst >> 12) & 0b00000111)) {
|
||||
case 0: op = rv_op_fmv_d_x; break;
|
||||
}
|
||||
break;
|
||||
case 123:
|
||||
switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
|
||||
switch (((inst >> 17) & 0b11111000) |
|
||||
((inst >> 12) & 0b00000111)) {
|
||||
case 0: op = rv_op_fmv_q_x; break;
|
||||
}
|
||||
break;
|
||||
@ -3224,9 +3277,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
|
||||
case 11: op = rv_op_vxor_vv; break;
|
||||
case 12: op = rv_op_vrgather_vv; break;
|
||||
case 14: op = rv_op_vrgatherei16_vv; break;
|
||||
case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vvm; break;
|
||||
case 16:
|
||||
if (((inst >> 25) & 1) == 0) {
|
||||
op = rv_op_vadc_vvm;
|
||||
}
|
||||
break;
|
||||
case 17: op = rv_op_vmadc_vvm; break;
|
||||
case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vvm; break;
|
||||
case 18:
|
||||
if (((inst >> 25) & 1) == 0) {
|
||||
op = rv_op_vsbc_vvm;
|
||||
}
|
||||
break;
|
||||
case 19: op = rv_op_vmsbc_vvm; break;
|
||||
case 23:
|
||||
if (((inst >> 20) & 0b111111) == 32)
|
||||
@ -3373,7 +3434,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
|
||||
case 2: op = rv_op_vmsof_m; break;
|
||||
case 3: op = rv_op_vmsif_m; break;
|
||||
case 16: op = rv_op_viota_m; break;
|
||||
case 17: if (((inst >> 20) & 0b11111) == 0) op = rv_op_vid_v; break;
|
||||
case 17:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
op = rv_op_vid_v;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
|
||||
@ -3423,7 +3488,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
|
||||
case 12: op = rv_op_vrgather_vi; break;
|
||||
case 14: op = rv_op_vslideup_vi; break;
|
||||
case 15: op = rv_op_vslidedown_vi; break;
|
||||
case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vim; break;
|
||||
case 16:
|
||||
if (((inst >> 25) & 1) == 0) {
|
||||
op = rv_op_vadc_vim;
|
||||
}
|
||||
break;
|
||||
case 17: op = rv_op_vmadc_vim; break;
|
||||
case 23:
|
||||
if (((inst >> 20) & 0b111111) == 32)
|
||||
@ -3473,9 +3542,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
|
||||
case 12: op = rv_op_vrgather_vx; break;
|
||||
case 14: op = rv_op_vslideup_vx; break;
|
||||
case 15: op = rv_op_vslidedown_vx; break;
|
||||
case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vxm; break;
|
||||
case 16:
|
||||
if (((inst >> 25) & 1) == 0) {
|
||||
op = rv_op_vadc_vxm;
|
||||
}
|
||||
break;
|
||||
case 17: op = rv_op_vmadc_vxm; break;
|
||||
case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vxm; break;
|
||||
case 18:
|
||||
if (((inst >> 25) & 1) == 0) {
|
||||
op = rv_op_vsbc_vxm;
|
||||
}
|
||||
break;
|
||||
case 19: op = rv_op_vmsbc_vxm; break;
|
||||
case 23:
|
||||
if (((inst >> 20) & 0b111111) == 32)
|
||||
@ -3646,7 +3723,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
|
||||
case 28:
|
||||
switch (((inst >> 12) & 0b111)) {
|
||||
case 0:
|
||||
switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) {
|
||||
switch (((inst >> 20) & 0b111111100000) |
|
||||
((inst >> 7) & 0b000000011111)) {
|
||||
case 0:
|
||||
switch (((inst >> 15) & 0b1111111111)) {
|
||||
case 0: op = rv_op_ecall; break;
|
||||
@ -3696,7 +3774,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
|
||||
}
|
||||
break;
|
||||
case 30:
|
||||
switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
|
||||
switch (((inst >> 22) & 0b1111111000) |
|
||||
((inst >> 12) & 0b0000000111)) {
|
||||
case 0: op = rv_op_addd; break;
|
||||
case 1: op = rv_op_slld; break;
|
||||
case 5: op = rv_op_srld; break;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user