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target/xtensa: update list of exception causes 

Add XEA2 exception cause codes defined in recent Xtensa ISA releases.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2019-04-18 16:36:36 -07:00
parent c884400f29
commit 98736654f3
1 changed files with 5 additions and 4 deletions
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9
target/xtensa/cpu.h
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@ -280,14 +280,15 @@ enum {
LEVEL1_INTERRUPT_CAUSE,
ALLOCA_CAUSE,
INTEGER_DIVIDE_BY_ZERO_CAUSE,
PRIVILEGED_CAUSE = 8,
PC_VALUE_ERROR_CAUSE,
PRIVILEGED_CAUSE,
LOAD_STORE_ALIGNMENT_CAUSE,
INSTR_PIF_DATA_ERROR_CAUSE = 12,
EXTERNAL_REG_PRIVILEGE_CAUSE,
EXCLUSIVE_ERROR_CAUSE,
INSTR_PIF_DATA_ERROR_CAUSE,
LOAD_STORE_PIF_DATA_ERROR_CAUSE,
INSTR_PIF_ADDR_ERROR_CAUSE,
LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
INST_TLB_MISS_CAUSE,
INST_TLB_MULTI_HIT_CAUSE,
INST_FETCH_PRIVILEGE_CAUSE,