target-hppa: Implement branches
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
b2167459ae
commit
98cd9ca7cc
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@ -455,6 +455,14 @@ static target_long low_sextract(uint32_t val, int pos, int len)
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return x;
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}
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static target_long assemble_12(uint32_t insn)
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{
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target_ulong x = -(target_ulong)(insn & 1);
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x = (x << 1) | extract32(insn, 2, 1);
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x = (x << 10) | extract32(insn, 3, 10);
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return x;
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}
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static target_long assemble_16(uint32_t insn)
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{
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/* Take the name from PA2.0, which produces a 16-bit number
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@ -463,6 +471,15 @@ static target_long assemble_16(uint32_t insn)
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return low_sextract(insn, 0, 14);
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}
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static target_long assemble_17(uint32_t insn)
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{
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target_ulong x = -(target_ulong)(insn & 1);
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x = (x << 5) | extract32(insn, 16, 5);
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x = (x << 1) | extract32(insn, 2, 1);
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x = (x << 10) | extract32(insn, 3, 10);
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return x << 2;
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}
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static target_long assemble_21(uint32_t insn)
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{
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target_ulong x = -(target_ulong)(insn & 1);
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@ -473,6 +490,15 @@ static target_long assemble_21(uint32_t insn)
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return x << 11;
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}
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static target_long assemble_22(uint32_t insn)
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{
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target_ulong x = -(target_ulong)(insn & 1);
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x = (x << 10) | extract32(insn, 16, 10);
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x = (x << 1) | extract32(insn, 2, 1);
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x = (x << 10) | extract32(insn, 3, 10);
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return x << 2;
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}
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/* The parisc documentation describes only the general interpretation of
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the conditions, without describing their exact implementation. The
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interpretations do not stand up well when considering ADD,C and SUB,B.
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@ -574,6 +600,24 @@ static DisasCond do_log_cond(unsigned cf, TCGv res)
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return do_cond(cf, res, res, res);
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}
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/* Similar, but for shift/extract/deposit conditions. */
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static DisasCond do_sed_cond(unsigned orig, TCGv res)
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{
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unsigned c, f;
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/* Convert the compressed condition codes to standard.
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0-2 are the same as logicals (nv,<,<=), while 3 is OD.
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4-7 are the reverse of 0-3. */
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c = orig & 3;
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if (c == 3) {
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c = 7;
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}
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f = (orig & 4) / 4;
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return do_log_cond(c * 2 + f, res);
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}
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/* Similar, but for unit conditions. */
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static DisasCond do_unit_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2)
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@ -897,6 +941,188 @@ static ExitStatus do_unit(DisasContext *ctx, unsigned rt, TCGv in1,
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return NO_EXIT;
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}
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/* Emit an unconditional branch to a direct target, which may or may not
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have already had nullification handled. */
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static ExitStatus do_dbranch(DisasContext *ctx, target_ulong dest,
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unsigned link, bool is_n)
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{
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if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) {
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if (link != 0) {
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copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
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}
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ctx->iaoq_n = dest;
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if (is_n) {
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ctx->null_cond.c = TCG_COND_ALWAYS;
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}
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return NO_EXIT;
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} else {
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nullify_over(ctx);
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if (link != 0) {
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copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
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}
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if (is_n && use_nullify_skip(ctx)) {
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nullify_set(ctx, 0);
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gen_goto_tb(ctx, 0, dest, dest + 4);
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} else {
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nullify_set(ctx, is_n);
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gen_goto_tb(ctx, 0, ctx->iaoq_b, dest);
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}
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nullify_end(ctx, NO_EXIT);
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nullify_set(ctx, 0);
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gen_goto_tb(ctx, 1, ctx->iaoq_b, ctx->iaoq_n);
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return EXIT_GOTO_TB;
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}
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}
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/* Emit a conditional branch to a direct target. If the branch itself
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is nullified, we should have already used nullify_over. */
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static ExitStatus do_cbranch(DisasContext *ctx, target_long disp, bool is_n,
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DisasCond *cond)
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{
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target_ulong dest = iaoq_dest(ctx, disp);
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TCGLabel *taken = NULL;
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TCGCond c = cond->c;
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int which = 0;
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bool n;
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assert(ctx->null_cond.c == TCG_COND_NEVER);
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/* Handle TRUE and NEVER as direct branches. */
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if (c == TCG_COND_ALWAYS) {
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return do_dbranch(ctx, dest, 0, is_n && disp >= 0);
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}
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if (c == TCG_COND_NEVER) {
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return do_dbranch(ctx, ctx->iaoq_n, 0, is_n && disp < 0);
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}
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taken = gen_new_label();
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cond_prep(cond);
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tcg_gen_brcond_tl(c, cond->a0, cond->a1, taken);
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cond_free(cond);
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/* Not taken: Condition not satisfied; nullify on backward branches. */
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n = is_n && disp < 0;
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if (n && use_nullify_skip(ctx)) {
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nullify_set(ctx, 0);
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gen_goto_tb(ctx, which++, ctx->iaoq_n, ctx->iaoq_n + 4);
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} else {
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if (!n && ctx->null_lab) {
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gen_set_label(ctx->null_lab);
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ctx->null_lab = NULL;
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}
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nullify_set(ctx, n);
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gen_goto_tb(ctx, which++, ctx->iaoq_b, ctx->iaoq_n);
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}
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gen_set_label(taken);
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/* Taken: Condition satisfied; nullify on forward branches. */
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n = is_n && disp >= 0;
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if (n && use_nullify_skip(ctx)) {
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nullify_set(ctx, 0);
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gen_goto_tb(ctx, which++, dest, dest + 4);
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} else {
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nullify_set(ctx, n);
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gen_goto_tb(ctx, which++, ctx->iaoq_b, dest);
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}
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/* Not taken: the branch itself was nullified. */
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if (ctx->null_lab) {
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gen_set_label(ctx->null_lab);
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ctx->null_lab = NULL;
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if (which < 2) {
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nullify_set(ctx, 0);
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gen_goto_tb(ctx, which, ctx->iaoq_b, ctx->iaoq_n);
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return EXIT_GOTO_TB;
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} else {
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return EXIT_IAQ_N_STALE;
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}
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} else {
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return EXIT_GOTO_TB;
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}
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}
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/* Emit an unconditional branch to an indirect target. This handles
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nullification of the branch itself. */
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static ExitStatus do_ibranch(DisasContext *ctx, TCGv dest,
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unsigned link, bool is_n)
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{
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TCGv a0, a1, next, tmp;
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TCGCond c;
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assert(ctx->null_lab == NULL);
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if (ctx->null_cond.c == TCG_COND_NEVER) {
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if (link != 0) {
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copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
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}
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next = get_temp(ctx);
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tcg_gen_mov_tl(next, dest);
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ctx->iaoq_n = -1;
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ctx->iaoq_n_var = next;
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if (is_n) {
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ctx->null_cond.c = TCG_COND_ALWAYS;
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}
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} else if (is_n && use_nullify_skip(ctx)) {
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/* The (conditional) branch, B, nullifies the next insn, N,
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and we're allowed to skip execution N (no single-step or
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tracepoint in effect). Since the exit_tb that we must use
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for the indirect branch consumes no special resources, we
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can (conditionally) skip B and continue execution. */
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/* The use_nullify_skip test implies we have a known control path. */
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tcg_debug_assert(ctx->iaoq_b != -1);
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tcg_debug_assert(ctx->iaoq_n != -1);
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/* We do have to handle the non-local temporary, DEST, before
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branching. Since IOAQ_F is not really live at this point, we
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can simply store DEST optimistically. Similarly with IAOQ_B. */
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tcg_gen_mov_tl(cpu_iaoq_f, dest);
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tcg_gen_addi_tl(cpu_iaoq_b, dest, 4);
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nullify_over(ctx);
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if (link != 0) {
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tcg_gen_movi_tl(cpu_gr[link], ctx->iaoq_n);
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}
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tcg_gen_exit_tb(0);
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return nullify_end(ctx, NO_EXIT);
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} else {
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cond_prep(&ctx->null_cond);
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c = ctx->null_cond.c;
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a0 = ctx->null_cond.a0;
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a1 = ctx->null_cond.a1;
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tmp = tcg_temp_new();
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next = get_temp(ctx);
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copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var);
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tcg_gen_movcond_tl(c, next, a0, a1, tmp, dest);
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ctx->iaoq_n = -1;
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ctx->iaoq_n_var = next;
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if (link != 0) {
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tcg_gen_movcond_tl(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp);
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}
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if (is_n) {
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/* The branch nullifies the next insn, which means the state of N
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after the branch is the inverse of the state of N that applied
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to the branch. */
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tcg_gen_setcond_tl(tcg_invert_cond(c), cpu_psw_n, a0, a1);
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cond_free(&ctx->null_cond);
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ctx->null_cond = cond_make_n();
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ctx->psw_n_nonzero = true;
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} else {
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cond_free(&ctx->null_cond);
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}
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}
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return NO_EXIT;
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}
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static ExitStatus trans_nop(DisasContext *ctx, uint32_t insn,
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const DisasInsn *di)
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{
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@ -1310,6 +1536,224 @@ static ExitStatus trans_ldo(DisasContext *ctx, uint32_t insn)
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return NO_EXIT;
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}
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static ExitStatus trans_cmpb(DisasContext *ctx, uint32_t insn,
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bool is_true, bool is_imm, bool is_dw)
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{
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target_long disp = assemble_12(insn) * 4;
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unsigned n = extract32(insn, 1, 1);
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unsigned c = extract32(insn, 13, 3);
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unsigned r = extract32(insn, 21, 5);
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unsigned cf = c * 2 + !is_true;
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TCGv dest, in1, in2, sv;
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DisasCond cond;
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nullify_over(ctx);
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if (is_imm) {
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in1 = load_const(ctx, low_sextract(insn, 16, 5));
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} else {
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in1 = load_gpr(ctx, extract32(insn, 16, 5));
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}
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in2 = load_gpr(ctx, r);
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dest = get_temp(ctx);
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tcg_gen_sub_tl(dest, in1, in2);
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TCGV_UNUSED(sv);
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if (c == 6) {
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sv = do_sub_sv(ctx, dest, in1, in2);
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}
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cond = do_sub_cond(cf, dest, in1, in2, sv);
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return do_cbranch(ctx, disp, n, &cond);
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}
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static ExitStatus trans_addb(DisasContext *ctx, uint32_t insn,
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bool is_true, bool is_imm)
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{
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target_long disp = assemble_12(insn) * 4;
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unsigned n = extract32(insn, 1, 1);
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unsigned c = extract32(insn, 13, 3);
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unsigned r = extract32(insn, 21, 5);
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unsigned cf = c * 2 + !is_true;
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TCGv dest, in1, in2, sv, cb_msb;
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DisasCond cond;
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nullify_over(ctx);
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if (is_imm) {
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in1 = load_const(ctx, low_sextract(insn, 16, 5));
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} else {
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in1 = load_gpr(ctx, extract32(insn, 16, 5));
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}
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in2 = load_gpr(ctx, r);
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dest = dest_gpr(ctx, r);
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TCGV_UNUSED(sv);
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TCGV_UNUSED(cb_msb);
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switch (c) {
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default:
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tcg_gen_add_tl(dest, in1, in2);
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break;
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case 4: case 5:
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cb_msb = get_temp(ctx);
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tcg_gen_movi_tl(cb_msb, 0);
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tcg_gen_add2_tl(dest, cb_msb, in1, cb_msb, in2, cb_msb);
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break;
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case 6:
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tcg_gen_add_tl(dest, in1, in2);
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sv = do_add_sv(ctx, dest, in1, in2);
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break;
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}
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cond = do_cond(cf, dest, cb_msb, sv);
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return do_cbranch(ctx, disp, n, &cond);
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}
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static ExitStatus trans_bb(DisasContext *ctx, uint32_t insn)
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{
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target_long disp = assemble_12(insn) * 4;
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unsigned n = extract32(insn, 1, 1);
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unsigned c = extract32(insn, 15, 1);
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unsigned r = extract32(insn, 16, 5);
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unsigned p = extract32(insn, 21, 5);
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unsigned i = extract32(insn, 26, 1);
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TCGv tmp, tcg_r;
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DisasCond cond;
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nullify_over(ctx);
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tmp = tcg_temp_new();
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tcg_r = load_gpr(ctx, r);
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if (i) {
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tcg_gen_shli_tl(tmp, tcg_r, p);
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} else {
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tcg_gen_shl_tl(tmp, tcg_r, cpu_sar);
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}
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cond = cond_make_0(c ? TCG_COND_GE : TCG_COND_LT, tmp);
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tcg_temp_free(tmp);
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return do_cbranch(ctx, disp, n, &cond);
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}
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static ExitStatus trans_movb(DisasContext *ctx, uint32_t insn, bool is_imm)
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{
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target_long disp = assemble_12(insn) * 4;
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unsigned n = extract32(insn, 1, 1);
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unsigned c = extract32(insn, 13, 3);
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unsigned t = extract32(insn, 16, 5);
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unsigned r = extract32(insn, 21, 5);
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TCGv dest;
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DisasCond cond;
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nullify_over(ctx);
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dest = dest_gpr(ctx, r);
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if (is_imm) {
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tcg_gen_movi_tl(dest, low_sextract(t, 0, 5));
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} else if (t == 0) {
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tcg_gen_movi_tl(dest, 0);
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} else {
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tcg_gen_mov_tl(dest, cpu_gr[t]);
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}
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cond = do_sed_cond(c, dest);
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return do_cbranch(ctx, disp, n, &cond);
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}
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static ExitStatus trans_be(DisasContext *ctx, uint32_t insn, bool is_l)
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{
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unsigned n = extract32(insn, 1, 1);
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unsigned b = extract32(insn, 21, 5);
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target_long disp = assemble_17(insn);
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/* unsigned s = low_uextract(insn, 13, 3); */
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/* ??? It seems like there should be a good way of using
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"be disp(sr2, r0)", the canonical gateway entry mechanism
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to our advantage. But that appears to be inconvenient to
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manage along side branch delay slots. Therefore we handle
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entry into the gateway page via absolute address. */
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/* Since we don't implement spaces, just branch. Do notice the special
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case of "be disp(*,r0)" using a direct branch to disp, so that we can
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goto_tb to the TB containing the syscall. */
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if (b == 0) {
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return do_dbranch(ctx, disp, is_l ? 31 : 0, n);
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} else {
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TCGv tmp = get_temp(ctx);
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tcg_gen_addi_tl(tmp, load_gpr(ctx, b), disp);
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return do_ibranch(ctx, tmp, is_l ? 31 : 0, n);
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}
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}
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static ExitStatus trans_bl(DisasContext *ctx, uint32_t insn,
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const DisasInsn *di)
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{
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unsigned n = extract32(insn, 1, 1);
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unsigned link = extract32(insn, 21, 5);
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target_long disp = assemble_17(insn);
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return do_dbranch(ctx, iaoq_dest(ctx, disp), link, n);
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}
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static ExitStatus trans_bl_long(DisasContext *ctx, uint32_t insn,
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const DisasInsn *di)
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{
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unsigned n = extract32(insn, 1, 1);
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target_long disp = assemble_22(insn);
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return do_dbranch(ctx, iaoq_dest(ctx, disp), 2, n);
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}
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static ExitStatus trans_blr(DisasContext *ctx, uint32_t insn,
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const DisasInsn *di)
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{
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unsigned n = extract32(insn, 1, 1);
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unsigned rx = extract32(insn, 16, 5);
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unsigned link = extract32(insn, 21, 5);
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TCGv tmp = get_temp(ctx);
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tcg_gen_shli_tl(tmp, load_gpr(ctx, rx), 3);
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tcg_gen_addi_tl(tmp, tmp, ctx->iaoq_f + 8);
|
||||
return do_ibranch(ctx, tmp, link, n);
|
||||
}
|
||||
|
||||
static ExitStatus trans_bv(DisasContext *ctx, uint32_t insn,
|
||||
const DisasInsn *di)
|
||||
{
|
||||
unsigned n = extract32(insn, 1, 1);
|
||||
unsigned rx = extract32(insn, 16, 5);
|
||||
unsigned rb = extract32(insn, 21, 5);
|
||||
TCGv dest;
|
||||
|
||||
if (rx == 0) {
|
||||
dest = load_gpr(ctx, rb);
|
||||
} else {
|
||||
dest = get_temp(ctx);
|
||||
tcg_gen_shli_tl(dest, load_gpr(ctx, rx), 3);
|
||||
tcg_gen_add_tl(dest, dest, load_gpr(ctx, rb));
|
||||
}
|
||||
return do_ibranch(ctx, dest, 0, n);
|
||||
}
|
||||
|
||||
static ExitStatus trans_bve(DisasContext *ctx, uint32_t insn,
|
||||
const DisasInsn *di)
|
||||
{
|
||||
unsigned n = extract32(insn, 1, 1);
|
||||
unsigned rb = extract32(insn, 21, 5);
|
||||
unsigned link = extract32(insn, 13, 1) ? 2 : 0;
|
||||
|
||||
return do_ibranch(ctx, load_gpr(ctx, rb), link, n);
|
||||
}
|
||||
|
||||
static const DisasInsn table_branch[] = {
|
||||
{ 0xe8000000u, 0xfc006000u, trans_bl }, /* B,L and B,L,PUSH */
|
||||
{ 0xe800a000u, 0xfc00e000u, trans_bl_long },
|
||||
{ 0xe8004000u, 0xfc00fffdu, trans_blr },
|
||||
{ 0xe800c000u, 0xfc00fffdu, trans_bv },
|
||||
{ 0xe800d000u, 0xfc00dffcu, trans_bve },
|
||||
};
|
||||
|
||||
static ExitStatus translate_table_int(DisasContext *ctx, uint32_t insn,
|
||||
const DisasInsn table[], size_t n)
|
||||
{
|
||||
|
|
@ -1338,13 +1782,46 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
|
|||
return trans_addil(ctx, insn);
|
||||
case 0x0D:
|
||||
return trans_ldo(ctx, insn);
|
||||
case 0x20:
|
||||
return trans_cmpb(ctx, insn, true, false, false);
|
||||
case 0x21:
|
||||
return trans_cmpb(ctx, insn, true, true, false);
|
||||
case 0x22:
|
||||
return trans_cmpb(ctx, insn, false, false, false);
|
||||
case 0x23:
|
||||
return trans_cmpb(ctx, insn, false, true, false);
|
||||
case 0x24:
|
||||
return trans_cmpiclr(ctx, insn);
|
||||
case 0x25:
|
||||
return trans_subi(ctx, insn);
|
||||
case 0x27:
|
||||
return trans_cmpb(ctx, insn, true, false, true);
|
||||
case 0x28:
|
||||
return trans_addb(ctx, insn, true, false);
|
||||
case 0x29:
|
||||
return trans_addb(ctx, insn, true, true);
|
||||
case 0x2A:
|
||||
return trans_addb(ctx, insn, false, false);
|
||||
case 0x2B:
|
||||
return trans_addb(ctx, insn, false, true);
|
||||
case 0x2C:
|
||||
case 0x2D:
|
||||
return trans_addi(ctx, insn);
|
||||
case 0x2F:
|
||||
return trans_cmpb(ctx, insn, false, false, true);
|
||||
case 0x30:
|
||||
case 0x31:
|
||||
return trans_bb(ctx, insn);
|
||||
case 0x32:
|
||||
return trans_movb(ctx, insn, false);
|
||||
case 0x33:
|
||||
return trans_movb(ctx, insn, true);
|
||||
case 0x38:
|
||||
return trans_be(ctx, insn, false);
|
||||
case 0x39:
|
||||
return trans_be(ctx, insn, true);
|
||||
case 0x3A:
|
||||
return translate_table(ctx, insn, table_branch);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue