hw/rdma: PVRDMA commands and data-path ops
First PVRDMA sub-module - implementation of the PVRDMA device. - PVRDMA commands such as create CQ and create MR. - Data path QP operations - post_send and post_recv. - Completion handler. Reviewed-by: Dotan Barak <dotanb@mellanox.com> Reviewed-by: Zhu Yanjun <yanjun.zhu@oracle.com> Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
This commit is contained in:
Yuval Shaia
Marcel Apfelbaum
parent
ef6d4ccdc9
commit
98d176f8e5
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@ -1,3 +1,5 @@
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ifeq ($(CONFIG_RDMA),y)
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obj-$(CONFIG_PCI) += rdma_utils.o rdma_backend.o rdma_rm.o
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obj-$(CONFIG_PCI) += vmw/pvrdma_dev_ring.o vmw/pvrdma_cmd.o \
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vmw/pvrdma_qp_ops.o
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endif
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@ -0,0 +1,122 @@
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/*
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* QEMU VMWARE paravirtual RDMA device definitions
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*
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* Copyright (C) 2018 Oracle
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* Copyright (C) 2018 Red Hat Inc
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*
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* Authors:
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* Yuval Shaia <yuval.shaia@oracle.com>
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* Marcel Apfelbaum <marcel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef PVRDMA_PVRDMA_H
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#define PVRDMA_PVRDMA_H
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#include <hw/pci/pci.h>
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#include <hw/pci/msix.h>
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#include "../rdma_backend_defs.h"
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#include "../rdma_rm_defs.h"
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#include <standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_ring.h>
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#include <standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h>
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#include "pvrdma_dev_ring.h"
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/* BARs */
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#define RDMA_MSIX_BAR_IDX 0
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#define RDMA_REG_BAR_IDX 1
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#define RDMA_UAR_BAR_IDX 2
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#define RDMA_BAR0_MSIX_SIZE (16 * 1024)
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#define RDMA_BAR1_REGS_SIZE 256
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#define RDMA_BAR2_UAR_SIZE (0x1000 * MAX_UCS) /* each uc gets page */
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/* MSIX */
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#define RDMA_MAX_INTRS 3
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#define RDMA_MSIX_TABLE 0x0000
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#define RDMA_MSIX_PBA 0x2000
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/* Interrupts Vectors */
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#define INTR_VEC_CMD_RING 0
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#define INTR_VEC_CMD_ASYNC_EVENTS 1
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#define INTR_VEC_CMD_COMPLETION_Q 2
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/* HW attributes */
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#define PVRDMA_HW_NAME "pvrdma"
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#define PVRDMA_HW_VERSION 17
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#define PVRDMA_FW_VERSION 14
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typedef struct DSRInfo {
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dma_addr_t dma;
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struct pvrdma_device_shared_region *dsr;
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union pvrdma_cmd_req *req;
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union pvrdma_cmd_resp *rsp;
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struct pvrdma_ring *async_ring_state;
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PvrdmaRing async;
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struct pvrdma_ring *cq_ring_state;
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PvrdmaRing cq;
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} DSRInfo;
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typedef struct PVRDMADev {
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PCIDevice parent_obj;
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MemoryRegion msix;
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MemoryRegion regs;
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uint32_t regs_data[RDMA_BAR1_REGS_SIZE];
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MemoryRegion uar;
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uint32_t uar_data[RDMA_BAR2_UAR_SIZE];
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DSRInfo dsr_info;
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int interrupt_mask;
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struct ibv_device_attr dev_attr;
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uint64_t node_guid;
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char *backend_device_name;
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uint8_t backend_gid_idx;
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uint8_t backend_port_num;
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RdmaBackendDev backend_dev;
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RdmaDeviceResources rdma_dev_res;
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} PVRDMADev;
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#define PVRDMA_DEV(dev) OBJECT_CHECK(PVRDMADev, (dev), PVRDMA_HW_NAME)
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static inline int get_reg_val(PVRDMADev *dev, hwaddr addr, uint32_t *val)
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{
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int idx = addr >> 2;
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if (idx > RDMA_BAR1_REGS_SIZE) {
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return -EINVAL;
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}
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*val = dev->regs_data[idx];
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return 0;
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}
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static inline int set_reg_val(PVRDMADev *dev, hwaddr addr, uint32_t val)
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{
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int idx = addr >> 2;
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if (idx > RDMA_BAR1_REGS_SIZE) {
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return -EINVAL;
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}
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dev->regs_data[idx] = val;
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return 0;
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}
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static inline void post_interrupt(PVRDMADev *dev, unsigned vector)
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{
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PCIDevice *pci_dev = PCI_DEVICE(dev);
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if (likely(!dev->interrupt_mask)) {
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msix_notify(pci_dev, vector);
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}
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}
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int execute_command(PVRDMADev *dev);
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#endif
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@ -0,0 +1,673 @@
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/*
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* QEMU paravirtual RDMA - Command channel
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*
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* Copyright (C) 2018 Oracle
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* Copyright (C) 2018 Red Hat Inc
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*
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* Authors:
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* Yuval Shaia <yuval.shaia@oracle.com>
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* Marcel Apfelbaum <marcel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include <qemu/osdep.h>
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#include <qemu/error-report.h>
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#include <cpu.h>
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#include <linux/types.h>
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#include "hw/hw.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_ids.h"
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#include "../rdma_backend.h"
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#include "../rdma_rm.h"
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#include "../rdma_utils.h"
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#include "pvrdma.h"
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#include <standard-headers/rdma/vmw_pvrdma-abi.h>
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static void *pvrdma_map_to_pdir(PCIDevice *pdev, uint64_t pdir_dma,
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uint32_t nchunks, size_t length)
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{
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uint64_t *dir, *tbl;
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int tbl_idx, dir_idx, addr_idx;
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void *host_virt = NULL, *curr_page;
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if (!nchunks) {
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pr_dbg("nchunks=0\n");
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return NULL;
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}
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dir = rdma_pci_dma_map(pdev, pdir_dma, TARGET_PAGE_SIZE);
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if (!dir) {
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error_report("PVRDMA: Failed to map to page directory");
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return NULL;
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}
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tbl = rdma_pci_dma_map(pdev, dir[0], TARGET_PAGE_SIZE);
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if (!tbl) {
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error_report("PVRDMA: Failed to map to page table 0");
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goto out_unmap_dir;
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}
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curr_page = rdma_pci_dma_map(pdev, (dma_addr_t)tbl[0], TARGET_PAGE_SIZE);
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if (!curr_page) {
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error_report("PVRDMA: Failed to map the first page");
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goto out_unmap_tbl;
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}
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host_virt = mremap(curr_page, 0, length, MREMAP_MAYMOVE);
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if (host_virt == MAP_FAILED) {
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host_virt = NULL;
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error_report("PVRDMA: Failed to remap memory for host_virt");
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goto out_unmap_tbl;
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}
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rdma_pci_dma_unmap(pdev, curr_page, TARGET_PAGE_SIZE);
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pr_dbg("host_virt=%p\n", host_virt);
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dir_idx = 0;
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tbl_idx = 1;
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addr_idx = 1;
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while (addr_idx < nchunks) {
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if ((tbl_idx == (TARGET_PAGE_SIZE / sizeof(uint64_t)))) {
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tbl_idx = 0;
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dir_idx++;
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pr_dbg("Mapping to table %d\n", dir_idx);
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rdma_pci_dma_unmap(pdev, tbl, TARGET_PAGE_SIZE);
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tbl = rdma_pci_dma_map(pdev, dir[dir_idx], TARGET_PAGE_SIZE);
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if (!tbl) {
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error_report("PVRDMA: Failed to map to page table %d", dir_idx);
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goto out_unmap_host_virt;
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}
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}
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pr_dbg("guest_dma[%d]=0x%lx\n", addr_idx, tbl[tbl_idx]);
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curr_page = rdma_pci_dma_map(pdev, (dma_addr_t)tbl[tbl_idx],
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TARGET_PAGE_SIZE);
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if (!curr_page) {
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error_report("PVRDMA: Failed to map to page %d, dir %d", tbl_idx,
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dir_idx);
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goto out_unmap_host_virt;
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}
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mremap(curr_page, 0, TARGET_PAGE_SIZE, MREMAP_MAYMOVE | MREMAP_FIXED,
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host_virt + TARGET_PAGE_SIZE * addr_idx);
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rdma_pci_dma_unmap(pdev, curr_page, TARGET_PAGE_SIZE);
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addr_idx++;
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tbl_idx++;
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}
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goto out_unmap_tbl;
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out_unmap_host_virt:
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munmap(host_virt, length);
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host_virt = NULL;
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out_unmap_tbl:
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rdma_pci_dma_unmap(pdev, tbl, TARGET_PAGE_SIZE);
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out_unmap_dir:
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rdma_pci_dma_unmap(pdev, dir, TARGET_PAGE_SIZE);
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return host_virt;
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}
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static int query_port(PVRDMADev *dev, union pvrdma_cmd_req *req,
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union pvrdma_cmd_resp *rsp)
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{
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struct pvrdma_cmd_query_port *cmd = &req->query_port;
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struct pvrdma_cmd_query_port_resp *resp = &rsp->query_port_resp;
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struct pvrdma_port_attr attrs = {0};
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pr_dbg("port=%d\n", cmd->port_num);
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if (rdma_backend_query_port(&dev->backend_dev,
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(struct ibv_port_attr *)&attrs)) {
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return -ENOMEM;
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}
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memset(resp, 0, sizeof(*resp));
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resp->hdr.response = cmd->hdr.response;
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resp->hdr.ack = PVRDMA_CMD_QUERY_PORT_RESP;
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resp->hdr.err = 0;
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resp->attrs.state = attrs.state;
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resp->attrs.max_mtu = attrs.max_mtu;
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resp->attrs.active_mtu = attrs.active_mtu;
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resp->attrs.phys_state = attrs.phys_state;
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resp->attrs.gid_tbl_len = MIN(MAX_PORT_GIDS, attrs.gid_tbl_len);
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resp->attrs.max_msg_sz = 1024;
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resp->attrs.pkey_tbl_len = MIN(MAX_PORT_PKEYS, attrs.pkey_tbl_len);
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resp->attrs.active_width = 1;
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resp->attrs.active_speed = 1;
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return 0;
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}
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static int query_pkey(PVRDMADev *dev, union pvrdma_cmd_req *req,
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union pvrdma_cmd_resp *rsp)
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{
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struct pvrdma_cmd_query_pkey *cmd = &req->query_pkey;
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struct pvrdma_cmd_query_pkey_resp *resp = &rsp->query_pkey_resp;
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pr_dbg("port=%d\n", cmd->port_num);
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pr_dbg("index=%d\n", cmd->index);
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memset(resp, 0, sizeof(*resp));
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resp->hdr.response = cmd->hdr.response;
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resp->hdr.ack = PVRDMA_CMD_QUERY_PKEY_RESP;
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resp->hdr.err = 0;
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resp->pkey = 0x7FFF;
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pr_dbg("pkey=0x%x\n", resp->pkey);
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return 0;
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}
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static int create_pd(PVRDMADev *dev, union pvrdma_cmd_req *req,
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union pvrdma_cmd_resp *rsp)
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{
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struct pvrdma_cmd_create_pd *cmd = &req->create_pd;
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struct pvrdma_cmd_create_pd_resp *resp = &rsp->create_pd_resp;
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pr_dbg("context=0x%x\n", cmd->ctx_handle ? cmd->ctx_handle : 0);
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memset(resp, 0, sizeof(*resp));
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resp->hdr.response = cmd->hdr.response;
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resp->hdr.ack = PVRDMA_CMD_CREATE_PD_RESP;
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resp->hdr.err = rdma_rm_alloc_pd(&dev->rdma_dev_res, &dev->backend_dev,
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&resp->pd_handle, cmd->ctx_handle);
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pr_dbg("ret=%d\n", resp->hdr.err);
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return resp->hdr.err;
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}
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static int destroy_pd(PVRDMADev *dev, union pvrdma_cmd_req *req,
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union pvrdma_cmd_resp *rsp)
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{
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struct pvrdma_cmd_destroy_pd *cmd = &req->destroy_pd;
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pr_dbg("pd_handle=%d\n", cmd->pd_handle);
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rdma_rm_dealloc_pd(&dev->rdma_dev_res, cmd->pd_handle);
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return 0;
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}
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static int create_mr(PVRDMADev *dev, union pvrdma_cmd_req *req,
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union pvrdma_cmd_resp *rsp)
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{
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struct pvrdma_cmd_create_mr *cmd = &req->create_mr;
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struct pvrdma_cmd_create_mr_resp *resp = &rsp->create_mr_resp;
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PCIDevice *pci_dev = PCI_DEVICE(dev);
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void *host_virt = NULL;
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memset(resp, 0, sizeof(*resp));
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resp->hdr.response = cmd->hdr.response;
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resp->hdr.ack = PVRDMA_CMD_CREATE_MR_RESP;
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pr_dbg("pd_handle=%d\n", cmd->pd_handle);
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pr_dbg("access_flags=0x%x\n", cmd->access_flags);
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pr_dbg("flags=0x%x\n", cmd->flags);
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if (!(cmd->flags & PVRDMA_MR_FLAG_DMA)) {
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host_virt = pvrdma_map_to_pdir(pci_dev, cmd->pdir_dma, cmd->nchunks,
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cmd->length);
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if (!host_virt) {
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pr_dbg("Failed to map to pdir\n");
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resp->hdr.err = -EINVAL;
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goto out;
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}
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}
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resp->hdr.err = rdma_rm_alloc_mr(&dev->rdma_dev_res, cmd->pd_handle,
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cmd->start, cmd->length, host_virt,
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cmd->access_flags, &resp->mr_handle,
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&resp->lkey, &resp->rkey);
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if (!resp->hdr.err) {
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munmap(host_virt, cmd->length);
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}
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out:
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pr_dbg("ret=%d\n", resp->hdr.err);
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return resp->hdr.err;
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}
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static int destroy_mr(PVRDMADev *dev, union pvrdma_cmd_req *req,
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union pvrdma_cmd_resp *rsp)
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{
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struct pvrdma_cmd_destroy_mr *cmd = &req->destroy_mr;
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pr_dbg("mr_handle=%d\n", cmd->mr_handle);
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rdma_rm_dealloc_mr(&dev->rdma_dev_res, cmd->mr_handle);
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return 0;
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}
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static int create_cq_ring(PCIDevice *pci_dev , PvrdmaRing **ring,
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uint64_t pdir_dma, uint32_t nchunks, uint32_t cqe)
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{
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uint64_t *dir = NULL, *tbl = NULL;
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PvrdmaRing *r;
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int rc = -EINVAL;
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char ring_name[MAX_RING_NAME_SZ];
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pr_dbg("pdir_dma=0x%llx\n", (long long unsigned int)pdir_dma);
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dir = rdma_pci_dma_map(pci_dev, pdir_dma, TARGET_PAGE_SIZE);
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if (!dir) {
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pr_dbg("Failed to map to CQ page directory\n");
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goto out;
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}
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tbl = rdma_pci_dma_map(pci_dev, dir[0], TARGET_PAGE_SIZE);
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if (!tbl) {
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pr_dbg("Failed to map to CQ page table\n");
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goto out;
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}
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r = g_malloc(sizeof(*r));
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*ring = r;
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r->ring_state = (struct pvrdma_ring *)
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rdma_pci_dma_map(pci_dev, tbl[0], TARGET_PAGE_SIZE);
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if (!r->ring_state) {
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pr_dbg("Failed to map to CQ ring state\n");
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goto out_free_ring;
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}
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sprintf(ring_name, "cq_ring_%lx", pdir_dma);
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rc = pvrdma_ring_init(r, ring_name, pci_dev, &r->ring_state[1],
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cqe, sizeof(struct pvrdma_cqe),
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/* first page is ring state */
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(dma_addr_t *)&tbl[1], nchunks - 1);
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if (rc) {
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goto out_unmap_ring_state;
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}
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goto out;
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out_unmap_ring_state:
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/* ring_state was in slot 1, not 0 so need to jump back */
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rdma_pci_dma_unmap(pci_dev, --r->ring_state, TARGET_PAGE_SIZE);
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out_free_ring:
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g_free(r);
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out:
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rdma_pci_dma_unmap(pci_dev, tbl, TARGET_PAGE_SIZE);
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rdma_pci_dma_unmap(pci_dev, dir, TARGET_PAGE_SIZE);
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return rc;
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}
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static int create_cq(PVRDMADev *dev, union pvrdma_cmd_req *req,
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union pvrdma_cmd_resp *rsp)
|
||||
{
|
||||
struct pvrdma_cmd_create_cq *cmd = &req->create_cq;
|
||||
struct pvrdma_cmd_create_cq_resp *resp = &rsp->create_cq_resp;
|
||||
PvrdmaRing *ring = NULL;
|
||||
|
||||
memset(resp, 0, sizeof(*resp));
|
||||
resp->hdr.response = cmd->hdr.response;
|
||||
resp->hdr.ack = PVRDMA_CMD_CREATE_CQ_RESP;
|
||||
|
||||
resp->cqe = cmd->cqe;
|
||||
|
||||
resp->hdr.err = create_cq_ring(PCI_DEVICE(dev), &ring, cmd->pdir_dma,
|
||||
cmd->nchunks, cmd->cqe);
|
||||
if (resp->hdr.err) {
|
||||
goto out;
|
||||
}
|
||||
|
||||
pr_dbg("ring=%p\n", ring);
|
||||
|
||||
resp->hdr.err = rdma_rm_alloc_cq(&dev->rdma_dev_res, &dev->backend_dev,
|
||||
cmd->cqe, &resp->cq_handle, ring);
|
||||
resp->cqe = cmd->cqe;
|
||||
|
||||
out:
|
||||
pr_dbg("ret=%d\n", resp->hdr.err);
|
||||
return resp->hdr.err;
|
||||
}
|
||||
|
||||
static int destroy_cq(PVRDMADev *dev, union pvrdma_cmd_req *req,
|
||||
union pvrdma_cmd_resp *rsp)
|
||||
{
|
||||
struct pvrdma_cmd_destroy_cq *cmd = &req->destroy_cq;
|
||||
RdmaRmCQ *cq;
|
||||
PvrdmaRing *ring;
|
||||
|
||||
pr_dbg("cq_handle=%d\n", cmd->cq_handle);
|
||||
|
||||
cq = rdma_rm_get_cq(&dev->rdma_dev_res, cmd->cq_handle);
|
||||
if (!cq) {
|
||||
pr_dbg("Invalid CQ handle\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ring = (PvrdmaRing *)cq->opaque;
|
||||
pvrdma_ring_free(ring);
|
||||
/* ring_state was in slot 1, not 0 so need to jump back */
|
||||
rdma_pci_dma_unmap(PCI_DEVICE(dev), --ring->ring_state, TARGET_PAGE_SIZE);
|
||||
g_free(ring);
|
||||
|
||||
rdma_rm_dealloc_cq(&dev->rdma_dev_res, cmd->cq_handle);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int create_qp_rings(PCIDevice *pci_dev, uint64_t pdir_dma,
|
||||
PvrdmaRing **rings, uint32_t scqe, uint32_t smax_sge,
|
||||
uint32_t spages, uint32_t rcqe, uint32_t rmax_sge,
|
||||
uint32_t rpages)
|
||||
{
|
||||
uint64_t *dir = NULL, *tbl = NULL;
|
||||
PvrdmaRing *sr, *rr;
|
||||
int rc = -EINVAL;
|
||||
char ring_name[MAX_RING_NAME_SZ];
|
||||
uint32_t wqe_sz;
|
||||
|
||||
pr_dbg("pdir_dma=0x%llx\n", (long long unsigned int)pdir_dma);
|
||||
dir = rdma_pci_dma_map(pci_dev, pdir_dma, TARGET_PAGE_SIZE);
|
||||
if (!dir) {
|
||||
pr_dbg("Failed to map to CQ page directory\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
tbl = rdma_pci_dma_map(pci_dev, dir[0], TARGET_PAGE_SIZE);
|
||||
if (!tbl) {
|
||||
pr_dbg("Failed to map to CQ page table\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
sr = g_malloc(2 * sizeof(*rr));
|
||||
rr = &sr[1];
|
||||
pr_dbg("sring=%p\n", sr);
|
||||
pr_dbg("rring=%p\n", rr);
|
||||
|
||||
*rings = sr;
|
||||
|
||||
pr_dbg("scqe=%d\n", scqe);
|
||||
pr_dbg("smax_sge=%d\n", smax_sge);
|
||||
pr_dbg("spages=%d\n", spages);
|
||||
pr_dbg("rcqe=%d\n", rcqe);
|
||||
pr_dbg("rmax_sge=%d\n", rmax_sge);
|
||||
pr_dbg("rpages=%d\n", rpages);
|
||||
|
||||
/* Create send ring */
|
||||
sr->ring_state = (struct pvrdma_ring *)
|
||||
rdma_pci_dma_map(pci_dev, tbl[0], TARGET_PAGE_SIZE);
|
||||
if (!sr->ring_state) {
|
||||
pr_dbg("Failed to map to CQ ring state\n");
|
||||
goto out_free_sr_mem;
|
||||
}
|
||||
|
||||
wqe_sz = pow2ceil(sizeof(struct pvrdma_sq_wqe_hdr) +
|
||||
sizeof(struct pvrdma_sge) * smax_sge - 1);
|
||||
|
||||
sprintf(ring_name, "qp_sring_%lx", pdir_dma);
|
||||
rc = pvrdma_ring_init(sr, ring_name, pci_dev, sr->ring_state,
|
||||
scqe, wqe_sz, (dma_addr_t *)&tbl[1], spages);
|
||||
if (rc) {
|
||||
goto out_unmap_ring_state;
|
||||
}
|
||||
|
||||
/* Create recv ring */
|
||||
rr->ring_state = &sr->ring_state[1];
|
||||
wqe_sz = pow2ceil(sizeof(struct pvrdma_rq_wqe_hdr) +
|
||||
sizeof(struct pvrdma_sge) * rmax_sge - 1);
|
||||
sprintf(ring_name, "qp_rring_%lx", pdir_dma);
|
||||
rc = pvrdma_ring_init(rr, ring_name, pci_dev, rr->ring_state,
|
||||
rcqe, wqe_sz, (dma_addr_t *)&tbl[1 + spages], rpages);
|
||||
if (rc) {
|
||||
goto out_free_sr;
|
||||
}
|
||||
|
||||
goto out;
|
||||
|
||||
out_free_sr:
|
||||
pvrdma_ring_free(sr);
|
||||
|
||||
out_unmap_ring_state:
|
||||
rdma_pci_dma_unmap(pci_dev, sr->ring_state, TARGET_PAGE_SIZE);
|
||||
|
||||
out_free_sr_mem:
|
||||
g_free(sr);
|
||||
|
||||
out:
|
||||
rdma_pci_dma_unmap(pci_dev, tbl, TARGET_PAGE_SIZE);
|
||||
rdma_pci_dma_unmap(pci_dev, dir, TARGET_PAGE_SIZE);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int create_qp(PVRDMADev *dev, union pvrdma_cmd_req *req,
|
||||
union pvrdma_cmd_resp *rsp)
|
||||
{
|
||||
struct pvrdma_cmd_create_qp *cmd = &req->create_qp;
|
||||
struct pvrdma_cmd_create_qp_resp *resp = &rsp->create_qp_resp;
|
||||
PvrdmaRing *rings = NULL;
|
||||
|
||||
memset(resp, 0, sizeof(*resp));
|
||||
resp->hdr.response = cmd->hdr.response;
|
||||
resp->hdr.ack = PVRDMA_CMD_CREATE_QP_RESP;
|
||||
|
||||
pr_dbg("total_chunks=%d\n", cmd->total_chunks);
|
||||
pr_dbg("send_chunks=%d\n", cmd->send_chunks);
|
||||
|
||||
resp->hdr.err = create_qp_rings(PCI_DEVICE(dev), cmd->pdir_dma, &rings,
|
||||
cmd->max_send_wr, cmd->max_send_sge,
|
||||
cmd->send_chunks, cmd->max_recv_wr,
|
||||
cmd->max_recv_sge, cmd->total_chunks -
|
||||
cmd->send_chunks - 1);
|
||||
if (resp->hdr.err) {
|
||||
goto out;
|
||||
}
|
||||
|
||||
pr_dbg("rings=%p\n", rings);
|
||||
|
||||
resp->hdr.err = rdma_rm_alloc_qp(&dev->rdma_dev_res, cmd->pd_handle,
|
||||
cmd->qp_type, cmd->max_send_wr,
|
||||
cmd->max_send_sge, cmd->send_cq_handle,
|
||||
cmd->max_recv_wr, cmd->max_recv_sge,
|
||||
cmd->recv_cq_handle, rings, &resp->qpn);
|
||||
|
||||
resp->max_send_wr = cmd->max_send_wr;
|
||||
resp->max_recv_wr = cmd->max_recv_wr;
|
||||
resp->max_send_sge = cmd->max_send_sge;
|
||||
resp->max_recv_sge = cmd->max_recv_sge;
|
||||
resp->max_inline_data = cmd->max_inline_data;
|
||||
|
||||
out:
|
||||
pr_dbg("ret=%d\n", resp->hdr.err);
|
||||
return resp->hdr.err;
|
||||
}
|
||||
|
||||
static int modify_qp(PVRDMADev *dev, union pvrdma_cmd_req *req,
|
||||
union pvrdma_cmd_resp *rsp)
|
||||
{
|
||||
struct pvrdma_cmd_modify_qp *cmd = &req->modify_qp;
|
||||
|
||||
pr_dbg("qp_handle=%d\n", cmd->qp_handle);
|
||||
|
||||
memset(rsp, 0, sizeof(*rsp));
|
||||
rsp->hdr.response = cmd->hdr.response;
|
||||
rsp->hdr.ack = PVRDMA_CMD_MODIFY_QP_RESP;
|
||||
|
||||
rsp->hdr.err = rdma_rm_modify_qp(&dev->rdma_dev_res, &dev->backend_dev,
|
||||
cmd->qp_handle, cmd->attr_mask,
|
||||
(union ibv_gid *)&cmd->attrs.ah_attr.grh.dgid,
|
||||
cmd->attrs.dest_qp_num, cmd->attrs.qp_state,
|
||||
cmd->attrs.qkey, cmd->attrs.rq_psn,
|
||||
cmd->attrs.sq_psn);
|
||||
|
||||
pr_dbg("ret=%d\n", rsp->hdr.err);
|
||||
return rsp->hdr.err;
|
||||
}
|
||||
|
||||
static int destroy_qp(PVRDMADev *dev, union pvrdma_cmd_req *req,
|
||||
union pvrdma_cmd_resp *rsp)
|
||||
{
|
||||
struct pvrdma_cmd_destroy_qp *cmd = &req->destroy_qp;
|
||||
RdmaRmQP *qp;
|
||||
PvrdmaRing *ring;
|
||||
|
||||
qp = rdma_rm_get_qp(&dev->rdma_dev_res, cmd->qp_handle);
|
||||
if (!qp) {
|
||||
pr_dbg("Invalid QP handle\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rdma_rm_dealloc_qp(&dev->rdma_dev_res, cmd->qp_handle);
|
||||
|
||||
ring = (PvrdmaRing *)qp->opaque;
|
||||
pr_dbg("sring=%p\n", &ring[0]);
|
||||
pvrdma_ring_free(&ring[0]);
|
||||
pr_dbg("rring=%p\n", &ring[1]);
|
||||
pvrdma_ring_free(&ring[1]);
|
||||
|
||||
rdma_pci_dma_unmap(PCI_DEVICE(dev), ring->ring_state, TARGET_PAGE_SIZE);
|
||||
g_free(ring);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int create_bind(PVRDMADev *dev, union pvrdma_cmd_req *req,
|
||||
union pvrdma_cmd_resp *rsp)
|
||||
{
|
||||
struct pvrdma_cmd_create_bind *cmd = &req->create_bind;
|
||||
#ifdef PVRDMA_DEBUG
|
||||
__be64 *subnet = (__be64 *)&cmd->new_gid[0];
|
||||
__be64 *if_id = (__be64 *)&cmd->new_gid[8];
|
||||
#endif
|
||||
|
||||
pr_dbg("index=%d\n", cmd->index);
|
||||
|
||||
if (cmd->index > MAX_PORT_GIDS) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pr_dbg("gid[%d]=0x%llx,0x%llx\n", cmd->index,
|
||||
(long long unsigned int)be64_to_cpu(*subnet),
|
||||
(long long unsigned int)be64_to_cpu(*if_id));
|
||||
|
||||
/* Driver forces to one port only */
|
||||
memcpy(dev->rdma_dev_res.ports[0].gid_tbl[cmd->index].raw, &cmd->new_gid,
|
||||
sizeof(cmd->new_gid));
|
||||
|
||||
/* TODO: Since drivers stores node_guid at load_dsr phase then this
|
||||
* assignment is not relevant, i need to figure out a way how to
|
||||
* retrieve MAC of our netdev */
|
||||
dev->node_guid = dev->rdma_dev_res.ports[0].gid_tbl[0].global.interface_id;
|
||||
pr_dbg("dev->node_guid=0x%llx\n",
|
||||
(long long unsigned int)be64_to_cpu(dev->node_guid));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int destroy_bind(PVRDMADev *dev, union pvrdma_cmd_req *req,
|
||||
union pvrdma_cmd_resp *rsp)
|
||||
{
|
||||
struct pvrdma_cmd_destroy_bind *cmd = &req->destroy_bind;
|
||||
|
||||
pr_dbg("clear index %d\n", cmd->index);
|
||||
|
||||
memset(dev->rdma_dev_res.ports[0].gid_tbl[cmd->index].raw, 0,
|
||||
sizeof(dev->rdma_dev_res.ports[0].gid_tbl[cmd->index].raw));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int create_uc(PVRDMADev *dev, union pvrdma_cmd_req *req,
|
||||
union pvrdma_cmd_resp *rsp)
|
||||
{
|
||||
struct pvrdma_cmd_create_uc *cmd = &req->create_uc;
|
||||
struct pvrdma_cmd_create_uc_resp *resp = &rsp->create_uc_resp;
|
||||
|
||||
pr_dbg("pfn=%d\n", cmd->pfn);
|
||||
|
||||
memset(resp, 0, sizeof(*resp));
|
||||
resp->hdr.response = cmd->hdr.response;
|
||||
resp->hdr.ack = PVRDMA_CMD_CREATE_UC_RESP;
|
||||
resp->hdr.err = rdma_rm_alloc_uc(&dev->rdma_dev_res, cmd->pfn,
|
||||
&resp->ctx_handle);
|
||||
|
||||
pr_dbg("ret=%d\n", resp->hdr.err);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int destroy_uc(PVRDMADev *dev, union pvrdma_cmd_req *req,
|
||||
union pvrdma_cmd_resp *rsp)
|
||||
{
|
||||
struct pvrdma_cmd_destroy_uc *cmd = &req->destroy_uc;
|
||||
|
||||
pr_dbg("ctx_handle=%d\n", cmd->ctx_handle);
|
||||
|
||||
rdma_rm_dealloc_uc(&dev->rdma_dev_res, cmd->ctx_handle);
|
||||
|
||||
return 0;
|
||||
}
|
||||
struct cmd_handler {
|
||||
uint32_t cmd;
|
||||
int (*exec)(PVRDMADev *dev, union pvrdma_cmd_req *req,
|
||||
union pvrdma_cmd_resp *rsp);
|
||||
};
|
||||
|
||||
static struct cmd_handler cmd_handlers[] = {
|
||||
{PVRDMA_CMD_QUERY_PORT, query_port},
|
||||
{PVRDMA_CMD_QUERY_PKEY, query_pkey},
|
||||
{PVRDMA_CMD_CREATE_PD, create_pd},
|
||||
{PVRDMA_CMD_DESTROY_PD, destroy_pd},
|
||||
{PVRDMA_CMD_CREATE_MR, create_mr},
|
||||
{PVRDMA_CMD_DESTROY_MR, destroy_mr},
|
||||
{PVRDMA_CMD_CREATE_CQ, create_cq},
|
||||
{PVRDMA_CMD_RESIZE_CQ, NULL},
|
||||
{PVRDMA_CMD_DESTROY_CQ, destroy_cq},
|
||||
{PVRDMA_CMD_CREATE_QP, create_qp},
|
||||
{PVRDMA_CMD_MODIFY_QP, modify_qp},
|
||||
{PVRDMA_CMD_QUERY_QP, NULL},
|
||||
{PVRDMA_CMD_DESTROY_QP, destroy_qp},
|
||||
{PVRDMA_CMD_CREATE_UC, create_uc},
|
||||
{PVRDMA_CMD_DESTROY_UC, destroy_uc},
|
||||
{PVRDMA_CMD_CREATE_BIND, create_bind},
|
||||
{PVRDMA_CMD_DESTROY_BIND, destroy_bind},
|
||||
};
|
||||
|
||||
int execute_command(PVRDMADev *dev)
|
||||
{
|
||||
int err = 0xFFFF;
|
||||
DSRInfo *dsr_info;
|
||||
|
||||
dsr_info = &dev->dsr_info;
|
||||
|
||||
pr_dbg("cmd=%d\n", dsr_info->req->hdr.cmd);
|
||||
if (dsr_info->req->hdr.cmd >= sizeof(cmd_handlers) /
|
||||
sizeof(struct cmd_handler)) {
|
||||
pr_dbg("Unsupported command\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (!cmd_handlers[dsr_info->req->hdr.cmd].exec) {
|
||||
pr_dbg("Unsupported command (not implemented yet)\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
err = cmd_handlers[dsr_info->req->hdr.cmd].exec(dev, dsr_info->req,
|
||||
dsr_info->rsp);
|
||||
out:
|
||||
set_reg_val(dev, PVRDMA_REG_ERR, err);
|
||||
post_interrupt(dev, INTR_VEC_CMD_RING);
|
||||
|
||||
return (err == 0) ? 0 : -EINVAL;
|
||||
}
|
||||
|
|
@ -0,0 +1,155 @@
|
|||
/*
|
||||
* QEMU paravirtual RDMA - Device rings
|
||||
*
|
||||
* Copyright (C) 2018 Oracle
|
||||
* Copyright (C) 2018 Red Hat Inc
|
||||
*
|
||||
* Authors:
|
||||
* Yuval Shaia <yuval.shaia@oracle.com>
|
||||
* Marcel Apfelbaum <marcel@redhat.com>
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <qemu/osdep.h>
|
||||
#include <hw/pci/pci.h>
|
||||
#include <cpu.h>
|
||||
|
||||
#include "../rdma_utils.h"
|
||||
#include <standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_ring.h>
|
||||
#include "pvrdma_dev_ring.h"
|
||||
|
||||
int pvrdma_ring_init(PvrdmaRing *ring, const char *name, PCIDevice *dev,
|
||||
struct pvrdma_ring *ring_state, uint32_t max_elems,
|
||||
size_t elem_sz, dma_addr_t *tbl, dma_addr_t npages)
|
||||
{
|
||||
int i;
|
||||
int rc = 0;
|
||||
|
||||
strncpy(ring->name, name, MAX_RING_NAME_SZ);
|
||||
ring->name[MAX_RING_NAME_SZ - 1] = 0;
|
||||
pr_dbg("Initializing %s ring\n", ring->name);
|
||||
ring->dev = dev;
|
||||
ring->ring_state = ring_state;
|
||||
ring->max_elems = max_elems;
|
||||
ring->elem_sz = elem_sz;
|
||||
pr_dbg("ring->elem_sz=%ld\n", ring->elem_sz);
|
||||
pr_dbg("npages=%ld\n", npages);
|
||||
/* TODO: Give a moment to think if we want to redo driver settings
|
||||
atomic_set(&ring->ring_state->prod_tail, 0);
|
||||
atomic_set(&ring->ring_state->cons_head, 0);
|
||||
*/
|
||||
ring->npages = npages;
|
||||
ring->pages = g_malloc(npages * sizeof(void *));
|
||||
|
||||
for (i = 0; i < npages; i++) {
|
||||
if (!tbl[i]) {
|
||||
pr_err("npages=%ld but tbl[%d] is NULL\n", (long)npages, i);
|
||||
continue;
|
||||
}
|
||||
|
||||
ring->pages[i] = rdma_pci_dma_map(dev, tbl[i], TARGET_PAGE_SIZE);
|
||||
if (!ring->pages[i]) {
|
||||
rc = -ENOMEM;
|
||||
pr_dbg("Failed to map to page %d\n", i);
|
||||
goto out_free;
|
||||
}
|
||||
memset(ring->pages[i], 0, TARGET_PAGE_SIZE);
|
||||
}
|
||||
|
||||
goto out;
|
||||
|
||||
out_free:
|
||||
while (i--) {
|
||||
rdma_pci_dma_unmap(dev, ring->pages[i], TARGET_PAGE_SIZE);
|
||||
}
|
||||
g_free(ring->pages);
|
||||
|
||||
out:
|
||||
return rc;
|
||||
}
|
||||
|
||||
void *pvrdma_ring_next_elem_read(PvrdmaRing *ring)
|
||||
{
|
||||
unsigned int idx = 0, offset;
|
||||
|
||||
/*
|
||||
pr_dbg("%s: t=%d, h=%d\n", ring->name, ring->ring_state->prod_tail,
|
||||
ring->ring_state->cons_head);
|
||||
*/
|
||||
|
||||
if (!pvrdma_idx_ring_has_data(ring->ring_state, ring->max_elems, &idx)) {
|
||||
pr_dbg("No more data in ring\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
offset = idx * ring->elem_sz;
|
||||
/*
|
||||
pr_dbg("idx=%d\n", idx);
|
||||
pr_dbg("offset=%d\n", offset);
|
||||
*/
|
||||
return ring->pages[offset / TARGET_PAGE_SIZE] + (offset % TARGET_PAGE_SIZE);
|
||||
}
|
||||
|
||||
void pvrdma_ring_read_inc(PvrdmaRing *ring)
|
||||
{
|
||||
pvrdma_idx_ring_inc(&ring->ring_state->cons_head, ring->max_elems);
|
||||
/*
|
||||
pr_dbg("%s: t=%d, h=%d, m=%ld\n", ring->name,
|
||||
ring->ring_state->prod_tail, ring->ring_state->cons_head,
|
||||
ring->max_elems);
|
||||
*/
|
||||
}
|
||||
|
||||
void *pvrdma_ring_next_elem_write(PvrdmaRing *ring)
|
||||
{
|
||||
unsigned int idx, offset, tail;
|
||||
|
||||
/*
|
||||
pr_dbg("%s: t=%d, h=%d\n", ring->name, ring->ring_state->prod_tail,
|
||||
ring->ring_state->cons_head);
|
||||
*/
|
||||
|
||||
if (!pvrdma_idx_ring_has_space(ring->ring_state, ring->max_elems, &tail)) {
|
||||
pr_dbg("CQ is full\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
idx = pvrdma_idx(&ring->ring_state->prod_tail, ring->max_elems);
|
||||
/* TODO: tail == idx */
|
||||
|
||||
offset = idx * ring->elem_sz;
|
||||
return ring->pages[offset / TARGET_PAGE_SIZE] + (offset % TARGET_PAGE_SIZE);
|
||||
}
|
||||
|
||||
void pvrdma_ring_write_inc(PvrdmaRing *ring)
|
||||
{
|
||||
pvrdma_idx_ring_inc(&ring->ring_state->prod_tail, ring->max_elems);
|
||||
/*
|
||||
pr_dbg("%s: t=%d, h=%d, m=%ld\n", ring->name,
|
||||
ring->ring_state->prod_tail, ring->ring_state->cons_head,
|
||||
ring->max_elems);
|
||||
*/
|
||||
}
|
||||
|
||||
void pvrdma_ring_free(PvrdmaRing *ring)
|
||||
{
|
||||
if (!ring) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (!ring->pages) {
|
||||
return;
|
||||
}
|
||||
|
||||
pr_dbg("ring->npages=%d\n", ring->npages);
|
||||
while (ring->npages--) {
|
||||
rdma_pci_dma_unmap(ring->dev, ring->pages[ring->npages],
|
||||
TARGET_PAGE_SIZE);
|
||||
}
|
||||
|
||||
g_free(ring->pages);
|
||||
ring->pages = NULL;
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* QEMU VMWARE paravirtual RDMA ring utilities
|
||||
*
|
||||
* Copyright (C) 2018 Oracle
|
||||
* Copyright (C) 2018 Red Hat Inc
|
||||
*
|
||||
* Authors:
|
||||
* Yuval Shaia <yuval.shaia@oracle.com>
|
||||
* Marcel Apfelbaum <marcel@redhat.com>
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PVRDMA_DEV_RING_H
|
||||
#define PVRDMA_DEV_RING_H
|
||||
|
||||
#include <qemu/typedefs.h>
|
||||
|
||||
#define MAX_RING_NAME_SZ 32
|
||||
|
||||
typedef struct PvrdmaRing {
|
||||
char name[MAX_RING_NAME_SZ];
|
||||
PCIDevice *dev;
|
||||
uint32_t max_elems;
|
||||
size_t elem_sz;
|
||||
struct pvrdma_ring *ring_state; /* used only for unmap */
|
||||
int npages;
|
||||
void **pages;
|
||||
} PvrdmaRing;
|
||||
|
||||
int pvrdma_ring_init(PvrdmaRing *ring, const char *name, PCIDevice *dev,
|
||||
struct pvrdma_ring *ring_state, uint32_t max_elems,
|
||||
size_t elem_sz, dma_addr_t *tbl, dma_addr_t npages);
|
||||
void *pvrdma_ring_next_elem_read(PvrdmaRing *ring);
|
||||
void pvrdma_ring_read_inc(PvrdmaRing *ring);
|
||||
void *pvrdma_ring_next_elem_write(PvrdmaRing *ring);
|
||||
void pvrdma_ring_write_inc(PvrdmaRing *ring);
|
||||
void pvrdma_ring_free(PvrdmaRing *ring);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,222 @@
|
|||
/*
|
||||
* QEMU paravirtual RDMA - QP implementation
|
||||
*
|
||||
* Copyright (C) 2018 Oracle
|
||||
* Copyright (C) 2018 Red Hat Inc
|
||||
*
|
||||
* Authors:
|
||||
* Yuval Shaia <yuval.shaia@oracle.com>
|
||||
* Marcel Apfelbaum <marcel@redhat.com>
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <qemu/osdep.h>
|
||||
|
||||
#include "../rdma_utils.h"
|
||||
#include "../rdma_rm.h"
|
||||
#include "../rdma_backend.h"
|
||||
|
||||
#include "pvrdma.h"
|
||||
#include <standard-headers/rdma/vmw_pvrdma-abi.h>
|
||||
#include "pvrdma_qp_ops.h"
|
||||
|
||||
typedef struct CompHandlerCtx {
|
||||
PVRDMADev *dev;
|
||||
uint32_t cq_handle;
|
||||
struct pvrdma_cqe cqe;
|
||||
} CompHandlerCtx;
|
||||
|
||||
/* Send Queue WQE */
|
||||
typedef struct PvrdmaSqWqe {
|
||||
struct pvrdma_sq_wqe_hdr hdr;
|
||||
struct pvrdma_sge sge[0];
|
||||
} PvrdmaSqWqe;
|
||||
|
||||
/* Recv Queue WQE */
|
||||
typedef struct PvrdmaRqWqe {
|
||||
struct pvrdma_rq_wqe_hdr hdr;
|
||||
struct pvrdma_sge sge[0];
|
||||
} PvrdmaRqWqe;
|
||||
|
||||
/*
|
||||
* 1. Put CQE on send CQ ring
|
||||
* 2. Put CQ number on dsr completion ring
|
||||
* 3. Interrupt host
|
||||
*/
|
||||
static int pvrdma_post_cqe(PVRDMADev *dev, uint32_t cq_handle,
|
||||
struct pvrdma_cqe *cqe)
|
||||
{
|
||||
struct pvrdma_cqe *cqe1;
|
||||
struct pvrdma_cqne *cqne;
|
||||
PvrdmaRing *ring;
|
||||
RdmaRmCQ *cq = rdma_rm_get_cq(&dev->rdma_dev_res, cq_handle);
|
||||
|
||||
if (unlikely(!cq)) {
|
||||
pr_dbg("Invalid cqn %d\n", cq_handle);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ring = (PvrdmaRing *)cq->opaque;
|
||||
pr_dbg("ring=%p\n", ring);
|
||||
|
||||
/* Step #1: Put CQE on CQ ring */
|
||||
pr_dbg("Writing CQE\n");
|
||||
cqe1 = pvrdma_ring_next_elem_write(ring);
|
||||
if (unlikely(!cqe1)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
cqe1->wr_id = cqe->wr_id;
|
||||
cqe1->qp = cqe->qp;
|
||||
cqe1->opcode = cqe->opcode;
|
||||
cqe1->status = cqe->status;
|
||||
cqe1->vendor_err = cqe->vendor_err;
|
||||
|
||||
pvrdma_ring_write_inc(ring);
|
||||
|
||||
/* Step #2: Put CQ number on dsr completion ring */
|
||||
pr_dbg("Writing CQNE\n");
|
||||
cqne = pvrdma_ring_next_elem_write(&dev->dsr_info.cq);
|
||||
if (unlikely(!cqne)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
cqne->info = cq_handle;
|
||||
pvrdma_ring_write_inc(&dev->dsr_info.cq);
|
||||
|
||||
pr_dbg("cq->notify=%d\n", cq->notify);
|
||||
if (cq->notify) {
|
||||
cq->notify = false;
|
||||
post_interrupt(dev, INTR_VEC_CMD_COMPLETION_Q);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pvrdma_qp_ops_comp_handler(int status, unsigned int vendor_err,
|
||||
void *ctx)
|
||||
{
|
||||
CompHandlerCtx *comp_ctx = (CompHandlerCtx *)ctx;
|
||||
|
||||
pr_dbg("cq_handle=%d\n", comp_ctx->cq_handle);
|
||||
pr_dbg("wr_id=%ld\n", comp_ctx->cqe.wr_id);
|
||||
pr_dbg("status=%d\n", status);
|
||||
pr_dbg("vendor_err=0x%x\n", vendor_err);
|
||||
comp_ctx->cqe.status = status;
|
||||
comp_ctx->cqe.vendor_err = vendor_err;
|
||||
pvrdma_post_cqe(comp_ctx->dev, comp_ctx->cq_handle, &comp_ctx->cqe);
|
||||
g_free(ctx);
|
||||
}
|
||||
|
||||
void pvrdma_qp_ops_fini(void)
|
||||
{
|
||||
rdma_backend_unregister_comp_handler();
|
||||
}
|
||||
|
||||
int pvrdma_qp_ops_init(void)
|
||||
{
|
||||
rdma_backend_register_comp_handler(pvrdma_qp_ops_comp_handler);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pvrdma_qp_send(PVRDMADev *dev, uint32_t qp_handle)
|
||||
{
|
||||
RdmaRmQP *qp;
|
||||
PvrdmaSqWqe *wqe;
|
||||
PvrdmaRing *ring;
|
||||
|
||||
pr_dbg("qp_handle=%d\n", qp_handle);
|
||||
|
||||
qp = rdma_rm_get_qp(&dev->rdma_dev_res, qp_handle);
|
||||
if (unlikely(!qp)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ring = (PvrdmaRing *)qp->opaque;
|
||||
pr_dbg("sring=%p\n", ring);
|
||||
|
||||
wqe = (struct PvrdmaSqWqe *)pvrdma_ring_next_elem_read(ring);
|
||||
while (wqe) {
|
||||
CompHandlerCtx *comp_ctx;
|
||||
|
||||
pr_dbg("wr_id=%ld\n", wqe->hdr.wr_id);
|
||||
|
||||
/* Prepare CQE */
|
||||
comp_ctx = g_malloc(sizeof(CompHandlerCtx));
|
||||
comp_ctx->dev = dev;
|
||||
comp_ctx->cq_handle = qp->send_cq_handle;
|
||||
comp_ctx->cqe.wr_id = wqe->hdr.wr_id;
|
||||
comp_ctx->cqe.qp = qp_handle;
|
||||
comp_ctx->cqe.opcode = wqe->hdr.opcode;
|
||||
|
||||
rdma_backend_post_send(&dev->backend_dev, &qp->backend_qp, qp->qp_type,
|
||||
(struct ibv_sge *)&wqe->sge[0], wqe->hdr.num_sge,
|
||||
(union ibv_gid *)wqe->hdr.wr.ud.av.dgid,
|
||||
wqe->hdr.wr.ud.remote_qpn,
|
||||
wqe->hdr.wr.ud.remote_qkey, comp_ctx);
|
||||
|
||||
pvrdma_ring_read_inc(ring);
|
||||
|
||||
wqe = pvrdma_ring_next_elem_read(ring);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pvrdma_qp_recv(PVRDMADev *dev, uint32_t qp_handle)
|
||||
{
|
||||
RdmaRmQP *qp;
|
||||
PvrdmaRqWqe *wqe;
|
||||
PvrdmaRing *ring;
|
||||
|
||||
pr_dbg("qp_handle=%d\n", qp_handle);
|
||||
|
||||
qp = rdma_rm_get_qp(&dev->rdma_dev_res, qp_handle);
|
||||
if (unlikely(!qp)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ring = &((PvrdmaRing *)qp->opaque)[1];
|
||||
pr_dbg("rring=%p\n", ring);
|
||||
|
||||
wqe = (struct PvrdmaRqWqe *)pvrdma_ring_next_elem_read(ring);
|
||||
while (wqe) {
|
||||
CompHandlerCtx *comp_ctx;
|
||||
|
||||
pr_dbg("wr_id=%ld\n", wqe->hdr.wr_id);
|
||||
|
||||
/* Prepare CQE */
|
||||
comp_ctx = g_malloc(sizeof(CompHandlerCtx));
|
||||
comp_ctx->dev = dev;
|
||||
comp_ctx->cq_handle = qp->recv_cq_handle;
|
||||
comp_ctx->cqe.qp = qp_handle;
|
||||
comp_ctx->cqe.wr_id = wqe->hdr.wr_id;
|
||||
|
||||
rdma_backend_post_recv(&dev->backend_dev, &dev->rdma_dev_res,
|
||||
&qp->backend_qp, qp->qp_type,
|
||||
(struct ibv_sge *)&wqe->sge[0], wqe->hdr.num_sge,
|
||||
comp_ctx);
|
||||
|
||||
pvrdma_ring_read_inc(ring);
|
||||
|
||||
wqe = pvrdma_ring_next_elem_read(ring);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void pvrdma_cq_poll(RdmaDeviceResources *dev_res, uint32_t cq_handle)
|
||||
{
|
||||
RdmaRmCQ *cq;
|
||||
|
||||
cq = rdma_rm_get_cq(dev_res, cq_handle);
|
||||
if (!cq) {
|
||||
pr_dbg("Invalid CQ# %d\n", cq_handle);
|
||||
}
|
||||
|
||||
rdma_backend_poll_cq(dev_res, &cq->backend_cq);
|
||||
}
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* QEMU VMWARE paravirtual RDMA QP Operations
|
||||
*
|
||||
* Copyright (C) 2018 Oracle
|
||||
* Copyright (C) 2018 Red Hat Inc
|
||||
*
|
||||
* Authors:
|
||||
* Yuval Shaia <yuval.shaia@oracle.com>
|
||||
* Marcel Apfelbaum <marcel@redhat.com>
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PVRDMA_QP_H
|
||||
#define PVRDMA_QP_H
|
||||
|
||||
#include "pvrdma.h"
|
||||
|
||||
int pvrdma_qp_ops_init(void);
|
||||
void pvrdma_qp_ops_fini(void);
|
||||
int pvrdma_qp_send(PVRDMADev *dev, uint32_t qp_handle);
|
||||
int pvrdma_qp_recv(PVRDMADev *dev, uint32_t qp_handle);
|
||||
void pvrdma_cq_poll(RdmaDeviceResources *dev_res, uint32_t cq_handle);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue