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target/ppc: Add infrastructure for prefixed insns 

Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210601193528.2533031-4-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Richard Henderson 2021-06-01 16:35:17 -03:00 committed by David Gibson
parent 64a0f6448c
commit 99082815f1
6 changed files with 95 additions and 6 deletions
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1
target/ppc/cpu.h
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@ -144,6 +144,7 @@ enum {
POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */
/* Exception subtypes for POWERPC_EXCP_PROGRAM */
/* FP exceptions */
POWERPC_EXCP_FP = 0x10,

18
target/ppc/insn32.decode Normal file
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@ -0,0 +1,18 @@
#
# Power ISA decode for 32-bit insns (opcode space 0)
#
# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2.1 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#

18
target/ppc/insn64.decode Normal file
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@ -0,0 +1,18 @@
#
# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1)
#
# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2.1 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#

9
target/ppc/meson.build
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@ -20,6 +20,15 @@ ppc_ss.add(when: 'CONFIG_TCG', if_true: files(
ppc_ss.add(libdecnumber)
gen = [
decodetree.process('insn32.decode',
extra_args: '--static-decode=decode_insn32'),
decodetree.process('insn64.decode',
extra_args: ['--static-decode=decode_insn64',
'--insnwidth=64']),
]
ppc_ss.add(gen)
ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c'))

37
target/ppc/translate.c
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@ -7690,6 +7690,10 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
#endif
#include "decode-insn32.c.inc"
#include "decode-insn64.c.inc"
#include "translate/fixedpoint-impl.c.inc"
#include "translate/fp-impl.c.inc"
#include "translate/vmx-impl.c.inc"
@ -8850,11 +8854,18 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
return true;
}
static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)
{
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
return opc1(insn) == 1;
}
static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = cs->env_ptr;
target_ulong pc;
uint32_t insn;
bool ok;
@ -8862,18 +8873,32 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
ctx->cia = ctx->base.pc_next;
insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx));
ctx->base.pc_next += 4;
ctx->cia = pc = ctx->base.pc_next;
insn = translator_ldl_swap(env, pc, need_byteswap(ctx));
ctx->base.pc_next = pc += 4;
ok = decode_legacy(cpu, ctx, insn);
if (!is_prefix_insn(ctx, insn)) {
ok = (decode_insn32(ctx, insn) ||
decode_legacy(cpu, ctx, insn));
} else if ((pc & 63) == 0) {
/*
* Power v3.1, section 1.9 Exceptions:
* attempt to execute a prefixed instruction that crosses a
* 64-byte address boundary (system alignment error).
*/
gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
ok = true;
} else {
uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx));
ctx->base.pc_next = pc += 4;
ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
}
if (!ok) {
gen_invalid(ctx);
}
/* End the TB when crossing a page boundary. */
if (ctx->base.is_jmp == DISAS_NEXT &&
!(ctx->base.pc_next & ~TARGET_PAGE_MASK)) {
if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) {
ctx->base.is_jmp = DISAS_TOO_MANY;
}

18
target/ppc/translate/fixedpoint-impl.c.inc Normal file
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@ -0,0 +1,18 @@
/*
* Power ISA decode for Fixed-Point Facility instructions
*
* Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/