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target/riscv: Remove RVB (replaced by Zb[abcs])

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With everything classified as Zb[abcs] and pre-0.93 draft-B
instructions that are not part of Zb[abcs] removed, we can remove the
remaining support code for RVB.

Note that RVB has been retired for good and misa.B will neither mean
'some' or 'all of' Zb*:
  https://lists.riscv.org/g/tech-bitmanip/message/532

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-16-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philipp Tomsich 2021-09-11 16:00:15 +02:00 committed by Alistair Francis
parent 06dfa8a5c5
commit 9916ea3c97
3 changed files with 0 additions and 33 deletions
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26
target/riscv/cpu.c
View File

@ -127,11 +127,6 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
env->priv_ver = priv_ver;
}
static void set_bext_version(CPURISCVState *env, int bext_ver)
{
env->bext_ver = bext_ver;
}
static void set_vext_version(CPURISCVState *env, int vext_ver)
{
env->vext_ver = vext_ver;
@ -496,25 +491,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
if (cpu->cfg.ext_b) {
int bext_version = BEXT_VERSION_0_93_0;
target_misa |= RVB;
if (cpu->cfg.bext_spec) {
if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
bext_version = BEXT_VERSION_0_93_0;
} else {
error_setg(errp,
"Unsupported bitmanip spec version '%s'",
cpu->cfg.bext_spec);
return;
}
} else {
qemu_log("bitmanip version is not specified, "
"use the default value v0.93\n");
}
set_bext_version(env, bext_version);
}
if (cpu->cfg.ext_v) {
int vext_version = VEXT_VERSION_0_07_1;
target_misa |= RVV;
@ -616,7 +592,6 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
@ -627,7 +602,6 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),

3
target/riscv/cpu.h
View File

@ -67,7 +67,6 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
#define RVB RV('B')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@ -83,7 +82,6 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
#define BEXT_VERSION_0_93_0 0x00009300
#define VEXT_VERSION_0_07_1 0x00000701
enum {
@ -288,7 +286,6 @@ struct RISCVCPU {
bool ext_f;
bool ext_d;
bool ext_c;
bool ext_b;
bool ext_s;
bool ext_u;
bool ext_h;

4
target/riscv/insn32.decode
View File

@ -712,10 +712,6 @@ rorw 0110000 .......... 101 ..... 0111011 @r
# instruction, so we use different handler functions to differentiate.
zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
# *** RV32B Standard Extension ***
# *** RV64B Standard Extension (in addition to RV32B) ***
# *** RV32 Zbc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r
clmulh 0000101 .......... 011 ..... 0110011 @r