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target/riscv: Remove the hardcoded HGATP_MODE macro 

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-04-24 13:31:55 +10:00
parent 5f10e6d895
commit 994b6bb2db
2 changed files with 15 additions and 20 deletions
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11
target/riscv/cpu_bits.h
View File

@ -195,17 +195,6 @@
#define CSR_HTIMEDELTA 0x605
#define CSR_HTIMEDELTAH 0x615
#if defined(TARGET_RISCV32)
#define HGATP_MODE SATP32_MODE
#define HGATP_VMID SATP32_ASID
#define HGATP_PPN SATP32_PPN
#endif
#if defined(TARGET_RISCV64)
#define HGATP_MODE SATP64_MODE
#define HGATP_VMID SATP64_ASID
#define HGATP_PPN SATP64_PPN
#endif
/* Virtual CSRs */
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204

24
target/riscv/cpu_helper.c
View File

@ -413,8 +413,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
widened = 0;
} else {
base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
vm = get_field(env->hgatp, HGATP_MODE);
if (riscv_cpu_is_32bit(env)) {
base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->hgatp, SATP32_MODE);
} else {
base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
vm = get_field(env->hgatp, SATP64_MODE);
}
widened = 2;
}
/* status.SUM will be ignored if execute on background */
@ -618,16 +623,17 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
bool first_stage, bool two_stage)
{
CPUState *cs = env_cpu(env);
int page_fault_exceptions;
int page_fault_exceptions, vm;
if (first_stage) {
page_fault_exceptions =
get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
!pmp_violation;
vm = get_field(env->satp, SATP_MODE);
} else if (riscv_cpu_is_32bit(env)) {
vm = get_field(env->hgatp, SATP32_MODE);
} else {
page_fault_exceptions =
get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
!pmp_violation;
vm = get_field(env->hgatp, SATP64_MODE);
}
page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
switch (access_type) {
case MMU_INST_FETCH:
if (riscv_cpu_virt_enabled(env) && !first_stage) {