target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
Allow user to set core's marchid, mvendorid, mipid CSRs through -cpu command line option. The default values of marchid and mipid are built with QEMU's version numbers. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220422040436.2233-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -34,6 +34,11 @@
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/* RISC-V CPU definitions */
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#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
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(QEMU_VERSION_MINOR << 8) | \
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(QEMU_VERSION_MICRO))
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#define RISCV_CPU_MIPID RISCV_CPU_MARCHID
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static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
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struct isa_ext_data {
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@ -810,6 +815,10 @@ static Property riscv_cpu_properties[] = {
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DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
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DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
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DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
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DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
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DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
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DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
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DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
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DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
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@ -393,6 +393,10 @@ struct RISCVCPUConfig {
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bool ext_zve32f;
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bool ext_zve64f;
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uint32_t mvendorid;
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uint64_t marchid;
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uint64_t mipid;
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/* Vendor-specific custom extensions */
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bool ext_XVentanaCondOps;
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@ -612,6 +612,36 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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CPUState *cs = env_cpu(env);
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RISCVCPU *cpu = RISCV_CPU(cs);
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*val = cpu->cfg.mvendorid;
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_marchid(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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CPUState *cs = env_cpu(env);
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RISCVCPU *cpu = RISCV_CPU(cs);
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*val = cpu->cfg.marchid;
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_mipid(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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CPUState *cs = env_cpu(env);
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RISCVCPU *cpu = RISCV_CPU(cs);
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*val = cpu->cfg.mipid;
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_mhartid(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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@ -3260,9 +3290,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
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/* Machine Information Registers */
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[CSR_MVENDORID] = { "mvendorid", any, read_zero },
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[CSR_MARCHID] = { "marchid", any, read_zero },
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[CSR_MIMPID] = { "mimpid", any, read_zero },
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[CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
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[CSR_MARCHID] = { "marchid", any, read_marchid },
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[CSR_MIMPID] = { "mimpid", any, read_mipid },
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[CSR_MHARTID] = { "mhartid", any, read_mhartid },
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[CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
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