target/arm: Drop EL3 no EL2 fallbacks
Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local vpidr_regs definition, and rely on the squashing to ARM_CP_CONST while registering for v8. This is a behavior change for v7 cpus with Security Extensions and without Virtualization Extensions, in that the virtualization cpregs are now correctly not present. This would be a migration compatibility break, except that we have an existing bug in which migration of 32-bit cpus with Security Extensions enabled does not work. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
696ba37718
commit
99a90811d0
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@ -5099,124 +5099,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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.fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
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};
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/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
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static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
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{ .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
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.access = PL2_RW,
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.readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
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{ .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
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.access = PL2_RW,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
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.access = PL2_RW,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
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.access = PL2_RW, .type = ARM_CP_CONST,
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.resetvalue = 0 },
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{ .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
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.access = PL2_RW, .type = ARM_CP_CONST,
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.resetvalue = 0 },
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{ .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
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.access = PL2_RW, .type = ARM_CP_CONST,
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.resetvalue = 0 },
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{ .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
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.access = PL2_RW, .type = ARM_CP_CONST,
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.resetvalue = 0 },
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{ .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
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.access = PL2_RW, .type = ARM_CP_CONST,
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.resetvalue = 0 },
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{ .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
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.access = PL2_RW, .accessfn = access_el3_aa32ns,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "VTTBR", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 6, .crm = 2,
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.access = PL2_RW, .accessfn = access_el3_aa32ns,
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.type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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{ .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
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.access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
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.resetvalue = 0 },
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{ .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
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.access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
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.resetvalue = 0 },
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{ .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
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.access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
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.resetvalue = 0 },
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{ .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
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.access = PL2_RW, .accessfn = access_tda,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
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.access = PL2_RW, .accessfn = access_el3_aa32ns,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
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.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "HIFAR", .state = ARM_CP_STATE_AA32,
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.type = ARM_CP_CONST,
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.cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
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.access = PL2_RW, .resetvalue = 0 },
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};
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/* Ditto, but for registers which exist in ARMv8 but not v7 */
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static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
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{ .name = "HCR2", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
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.access = PL2_RW,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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};
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static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
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{
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ARMCPU *cpu = env_archcpu(env);
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@ -7902,7 +7784,17 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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define_arm_cp_regs(cpu, v8_idregs);
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define_arm_cp_regs(cpu, v8_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_EL2)) {
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/*
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* Register the base EL2 cpregs.
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* Pre v8, these registers are implemented only as part of the
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* Virtualization Extensions (EL2 present). Beginning with v8,
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* if EL2 is missing but EL3 is enabled, mostly these become
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* RES0 from EL3, with some specific exceptions.
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*/
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if (arm_feature(env, ARM_FEATURE_EL2)
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|| (arm_feature(env, ARM_FEATURE_EL3)
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&& arm_feature(env, ARM_FEATURE_V8))) {
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uint64_t vmpidr_def = mpidr_read_val(env);
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ARMCPRegInfo vpidr_regs[] = {
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{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
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@ -7946,33 +7838,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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};
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define_one_arm_cp_reg(cpu, &rvbar);
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}
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} else {
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/* If EL2 is missing but higher ELs are enabled, we need to
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* register the no_el2 reginfos.
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*/
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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/* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
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* of MIDR_EL1 and MPIDR_EL1.
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*/
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ARMCPRegInfo vpidr_regs[] = {
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{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
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.access = PL2_RW, .accessfn = access_el3_aa32ns,
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.type = ARM_CP_CONST, .resetvalue = cpu->midr,
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.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
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{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
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.access = PL2_RW, .accessfn = access_el3_aa32ns,
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.type = ARM_CP_NO_RAW,
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.writefn = arm_cp_write_ignore, .readfn = mpidr_read },
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};
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define_arm_cp_regs(cpu, vpidr_regs);
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define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
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if (arm_feature(env, ARM_FEATURE_V8)) {
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define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
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}
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}
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}
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/* Register the base EL3 cpregs. */
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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define_arm_cp_regs(cpu, el3_cp_reginfo);
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ARMCPRegInfo el3_regs[] = {
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