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- Re-org accel/ and softmmu/ to have more target-agnostic objects. 

- Use CPUArchState as an abstract type, defined by each target
   (CPUState is our interface with generic code, CPUArchState is
    our interface with target-specific code).
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Merge remote-tracking branch 'remotes/philmd/tags/abstract-arch-cpu-20220307' into staging

- Re-org accel/ and softmmu/ to have more target-agnostic objects.

- Use CPUArchState as an abstract type, defined by each target
  (CPUState is our interface with generic code, CPUArchState is
   our interface with target-specific code).

# gpg: Signature made Sun 06 Mar 2022 23:23:19 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/abstract-arch-cpu-20220307: (33 commits)
  accel/tcg: Remove pointless CPUArchState casts
  target/i386: Remove pointless CPUArchState casts
  target: Use ArchCPU as interface to target CPU
  target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro
  target: Use CPUArchState as interface to target-specific CPU state
  target: Use forward declared type instead of structure type
  target/hexagon: Add missing 'hw/core/cpu.h' include
  target: Include missing 'cpu.h'
  Hexagon (target/hexagon) convert to OBJECT_DECLARE_TYPE
  target/i386/tcg/sysemu: Include missing 'exec/exec-all.h' header
  cpu: Add missing 'exec/exec-all.h' and 'qemu/accel.h' headers
  exec/cpu_ldst: Include 'cpu.h' to get target_ulong definition
  meson: Display libfdt as disabled when system emulation is disabled
  softmmu: Build target-agnostic objects once
  softmmu: Add qemu_init_arch_modules()
  exec/cpu: Make address_space_init/reloading_memory_map target agnostic
  exec/gdbstub: Make gdb_exit() / gdb_set_stop_cpu() target agnostic
  misc: Add missing "sysemu/cpu-timers.h" include
  misc: Remove unnecessary "sysemu/cpu-timers.h" include
  softmmu/cpu-timers: Remove unused 'exec/exec-all.h' header
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2022-03-07 19:07:44 +00:00
parent b49872aa8f 61deada4bf
commit 99c4a9e68e
87 changed files with 371 additions and 402 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
accel/kvm/kvm-accel-ops.c
View File

@ -74,11 +74,23 @@ static void kvm_start_vcpu_thread(CPUState *cpu)
cpu, QEMU_THREAD_JOINABLE);
}
static bool kvm_vcpu_thread_is_idle(CPUState *cpu)
{
return !kvm_halt_in_kernel();
}
static bool kvm_cpus_are_resettable(void)
{
return !kvm_enabled() || kvm_cpu_check_are_resettable();
}
static void kvm_accel_ops_class_init(ObjectClass *oc, void *data)
{
AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
ops->create_vcpu_thread = kvm_start_vcpu_thread;
ops->cpu_thread_is_idle = kvm_vcpu_thread_is_idle;
ops->cpus_are_resettable = kvm_cpus_are_resettable;
ops->synchronize_post_reset = kvm_cpu_synchronize_post_reset;
ops->synchronize_post_init = kvm_cpu_synchronize_post_init;
ops->synchronize_state = kvm_cpu_synchronize_state;

12
accel/meson.build
View File

@ -2,12 +2,14 @@ specific_ss.add(files('accel-common.c'))
softmmu_ss.add(files('accel-softmmu.c'))
user_ss.add(files('accel-user.c'))
subdir('hvf')
subdir('qtest')
subdir('kvm')
subdir('tcg')
subdir('xen')
subdir('stubs')
if have_system
subdir('hvf')
subdir('qtest')
subdir('kvm')
subdir('xen')
subdir('stubs')
endif
dummy_ss = ss.source_set()
dummy_ss.add(files(

1
accel/qtest/qtest.c
View File

@ -20,7 +20,6 @@
#include "qemu/accel.h"
#include "sysemu/qtest.h"
#include "sysemu/cpus.h"
#include "sysemu/cpu-timers.h"
#include "qemu/guest-random.h"
#include "qemu/main-loop.h"
#include "hw/core/cpu.h"

2
accel/stubs/hax-stub.c
View File

@ -16,6 +16,8 @@
#include "qemu/osdep.h"
#include "sysemu/hax.h"
bool hax_allowed;
int hax_sync_vcpus(void)
{
return 0;

5
accel/stubs/kvm-stub.c
View File

@ -12,10 +12,7 @@
#include "qemu/osdep.h"
#include "sysemu/kvm.h"
#ifndef CONFIG_USER_ONLY
#include "hw/pci/msi.h"
#endif
KVMState *kvm_state;
bool kvm_kernel_irqchip;
@ -80,7 +77,6 @@ int kvm_on_sigbus(int code, void *addr)
return 1;
}
#ifndef CONFIG_USER_ONLY
int kvm_irqchip_add_msi_route(KVMState *s, int vector, PCIDevice *dev)
{
return -ENOSYS;
@ -152,4 +148,3 @@ bool kvm_dirty_ring_enabled(void)
{
return false;
}
#endif

11
accel/stubs/meson.build
View File

@ -1,4 +1,7 @@
specific_ss.add(when: 'CONFIG_HAX', if_false: files('hax-stub.c'))
specific_ss.add(when: 'CONFIG_XEN', if_false: files('xen-stub.c'))
specific_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
specific_ss.add(when: 'CONFIG_TCG', if_false: files('tcg-stub.c'))
sysemu_stubs_ss = ss.source_set()
sysemu_stubs_ss.add(when: 'CONFIG_HAX', if_false: files('hax-stub.c'))
sysemu_stubs_ss.add(when: 'CONFIG_XEN', if_false: files('xen-stub.c'))
sysemu_stubs_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
sysemu_stubs_ss.add(when: 'CONFIG_TCG', if_false: files('tcg-stub.c'))
specific_ss.add_all(when: ['CONFIG_SOFTMMU'], if_true: sysemu_stubs_ss)

4
accel/tcg/cpu-exec.c
View File

@ -422,7 +422,7 @@ static void cpu_exec_exit(CPUState *cpu)
void cpu_exec_step_atomic(CPUState *cpu)
{
CPUArchState *env = (CPUArchState *)cpu->env_ptr;
CPUArchState *env = cpu->env_ptr;
TranslationBlock *tb;
target_ulong cs_base, pc;
uint32_t flags, cflags;
@ -532,7 +532,7 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
struct tb_desc desc;
uint32_t h;
desc.env = (CPUArchState *)cpu->env_ptr;
desc.env = cpu->env_ptr;
desc.cs_base = cs_base;
desc.flags = flags;
desc.cflags = cflags;

1
accel/tcg/tcg-accel-ops-icount.c
View File

@ -27,6 +27,7 @@
#include "qemu-common.h"
#include "sysemu/tcg.h"
#include "sysemu/replay.h"
#include "sysemu/cpu-timers.h"
#include "qemu/main-loop.h"
#include "qemu/guest-random.h"
#include "exec/exec-all.h"

1
accel/tcg/tcg-accel-ops-mttcg.c
View File

@ -27,6 +27,7 @@
#include "qemu-common.h"
#include "sysemu/tcg.h"
#include "sysemu/replay.h"
#include "sysemu/cpu-timers.h"
#include "qemu/main-loop.h"
#include "qemu/notify.h"
#include "qemu/guest-random.h"

1
accel/tcg/tcg-accel-ops-rr.c
View File

@ -27,6 +27,7 @@
#include "qemu-common.h"
#include "sysemu/tcg.h"
#include "sysemu/replay.h"
#include "sysemu/cpu-timers.h"
#include "qemu/main-loop.h"
#include "qemu/notify.h"
#include "qemu/guest-random.h"

1
accel/tcg/tcg-accel-ops.c
View File

@ -29,6 +29,7 @@
#include "qemu-common.h"
#include "sysemu/tcg.h"
#include "sysemu/replay.h"
#include "sysemu/cpu-timers.h"
#include "qemu/main-loop.h"
#include "qemu/guest-random.h"
#include "exec/exec-all.h"

8
cpu.c
View File

@ -35,10 +35,12 @@
#include "sysemu/tcg.h"
#include "sysemu/kvm.h"
#include "sysemu/replay.h"
#include "exec/exec-all.h"
#include "exec/translate-all.h"
#include "exec/log.h"
#include "hw/core/accel-cpu.h"
#include "trace/trace-root.h"
#include "qemu/accel.h"
uintptr_t qemu_host_page_size;
intptr_t qemu_host_page_mask;
@ -415,11 +417,11 @@ void cpu_abort(CPUState *cpu, const char *fmt, ...)
/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
void *ptr, target_ulong len, bool is_write)
int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
void *ptr, size_t len, bool is_write)
{
int flags;
target_ulong l, page;
vaddr l, page;
void * p;
uint8_t *buf = ptr;

4
include/exec/cpu-all.h
View File

@ -433,10 +433,6 @@ int cpu_exec(CPUState *cpu);
void tcg_exec_realizefn(CPUState *cpu, Error **errp);
void tcg_exec_unrealizefn(CPUState *cpu);
/* Returns: 0 on success, -1 on error */
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
void *ptr, target_ulong len, bool is_write);
/**
* cpu_set_cpustate_pointers(cpu)
* @cpu: The cpu object

39
include/exec/cpu-common.h
View File

@ -7,6 +7,18 @@
#include "exec/hwaddr.h"
#endif
/**
* vaddr:
* Type wide enough to contain any #target_ulong virtual address.
*/
typedef uint64_t vaddr;
#define VADDR_PRId PRId64
#define VADDR_PRIu PRIu64
#define VADDR_PRIo PRIo64
#define VADDR_PRIx PRIx64
#define VADDR_PRIX PRIX64
#define VADDR_MAX UINT64_MAX
/* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
* when intptr_t is 32-bit and we are aligning a long long.
*/
@ -78,6 +90,28 @@ void qemu_ram_unset_migratable(RAMBlock *rb);
size_t qemu_ram_pagesize(RAMBlock *block);
size_t qemu_ram_pagesize_largest(void);
/**
* cpu_address_space_init:
* @cpu: CPU to add this address space to
* @asidx: integer index of this address space
* @prefix: prefix to be used as name of address space
* @mr: the root memory region of address space
*
* Add the specified address space to the CPU's cpu_ases list.
* The address space added with @asidx 0 is the one used for the
* convenience pointer cpu->as.
* The target-specific code which registers ASes is responsible
* for defining what semantics address space 0, 1, 2, etc have.
*
* Before the first call to this function, the caller must set
* cpu->num_ases to the total number of address spaces it needs
* to support.
*
* Note that with KVM only one address space is supported.
*/
void cpu_address_space_init(CPUState *cpu, int asidx,
const char *prefix, MemoryRegion *mr);
void cpu_physical_memory_rw(hwaddr addr, void *buf,
hwaddr len, bool is_write);
static inline void cpu_physical_memory_read(hwaddr addr,
@ -90,6 +124,7 @@ static inline void cpu_physical_memory_write(hwaddr addr,
{
cpu_physical_memory_rw(addr, (void *)buf, len, true);
}
void cpu_reloading_memory_map(void);
void *cpu_physical_memory_map(hwaddr addr,
hwaddr *plen,
bool is_write);
@ -116,6 +151,10 @@ int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
#endif
/* Returns: 0 on success, -1 on error */
int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
void *ptr, size_t len, bool is_write);
/* vl.c */
extern int singlestep;

1
include/exec/cpu_ldst.h
View File

@ -64,6 +64,7 @@
#include "exec/memopidx.h"
#include "qemu/int128.h"
#include "cpu.h"
#if defined(CONFIG_USER_ONLY)
/* sparc32plus has 64bit long but 32bit space address

26
include/exec/exec-all.h
View File

@ -24,7 +24,6 @@
#ifdef CONFIG_TCG
#include "exec/cpu_ldst.h"
#endif
#include "sysemu/cpu-timers.h"
/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS
@ -81,31 +80,6 @@ static inline bool cpu_loop_exit_requested(CPUState *cpu)
return (int32_t)qatomic_read(&cpu_neg(cpu)->icount_decr.u32) < 0;
}
#if !defined(CONFIG_USER_ONLY)
void cpu_reloading_memory_map(void);
/**
* cpu_address_space_init:
* @cpu: CPU to add this address space to
* @asidx: integer index of this address space
* @prefix: prefix to be used as name of address space
* @mr: the root memory region of address space
*
* Add the specified address space to the CPU's cpu_ases list.
* The address space added with @asidx 0 is the one used for the
* convenience pointer cpu->as.
* The target-specific code which registers ASes is responsible
* for defining what semantics address space 0, 1, 2, etc have.
*
* Before the first call to this function, the caller must set
* cpu->num_ases to the total number of address spaces it needs
* to support.
*
* Note that with KVM only one address space is supported.
*/
void cpu_address_space_init(CPUState *cpu, int asidx,
const char *prefix, MemoryRegion *mr);
#endif
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* cputlb.c */
/**

25
include/exec/gdbstub.h
View File

@ -45,17 +45,6 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...);
*/
void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va);
int use_gdb_syscalls(void);
void gdb_set_stop_cpu(CPUState *cpu);
/**
* gdb_exit: exit gdb session, reporting inferior status
* @code: exit code reported
*
* This closes the session and sends a final packet to GDB reporting
* the exit status of the program. It also cleans up any connections
* detritus before returning.
*/
void gdb_exit(int code);
#ifdef CONFIG_USER_ONLY
/**
@ -165,7 +154,7 @@ static inline uint8_t * gdb_get_reg_ptr(GByteArray *buf, int len)
#define ldtul_p(addr) ldl_p(addr)
#endif
#endif
#endif /* NEED_CPU_H */
/**
* gdbserver_start: start the gdb server
@ -177,6 +166,18 @@ static inline uint8_t * gdb_get_reg_ptr(GByteArray *buf, int len)
*/
int gdbserver_start(const char *port_or_device);
/**
* gdb_exit: exit gdb session, reporting inferior status
* @code: exit code reported
*
* This closes the session and sends a final packet to GDB reporting
* the exit status of the program. It also cleans up any connections
* detritus before returning.
*/
void gdb_exit(int code);
void gdb_set_stop_cpu(CPUState *cpu);
/**
* gdb_has_xml:
* This is an ugly hack to cope with both new and old gdb.

2
include/exec/poison.h
View File

@ -51,8 +51,6 @@
#pragma GCC poison TARGET_PAGE_BITS
#pragma GCC poison TARGET_PAGE_ALIGN
#pragma GCC poison CPUArchState
#pragma GCC poison CPU_INTERRUPT_HARD
#pragma GCC poison CPU_INTERRUPT_EXITTB
#pragma GCC poison CPU_INTERRUPT_HALT

33
include/hw/core/cpu.h
View File

@ -22,6 +22,7 @@
#include "hw/qdev-core.h"
#include "disas/dis-asm.h"
#include "exec/cpu-common.h"
#include "exec/hwaddr.h"
#include "exec/memattrs.h"
#include "qapi/qapi-types-run-state.h"
@ -35,18 +36,6 @@
typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
void *opaque);
/**
* vaddr:
* Type wide enough to contain any #target_ulong virtual address.
*/
typedef uint64_t vaddr;
#define VADDR_PRId PRId64
#define VADDR_PRIu PRIu64
#define VADDR_PRIo PRIo64
#define VADDR_PRIx PRIx64
#define VADDR_PRIX PRIX64
#define VADDR_MAX UINT64_MAX
/**
* SECTION:cpu
* @section_id: QEMU-cpu
@ -66,6 +55,24 @@ typedef struct CPUClass CPUClass;
DECLARE_CLASS_CHECKERS(CPUClass, CPU,
TYPE_CPU)
/**
* OBJECT_DECLARE_CPU_TYPE:
* @CpuInstanceType: instance struct name
* @CpuClassType: class struct name
* @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators
*
* This macro is typically used in "cpu-qom.h" header file, and will:
*
* - create the typedefs for the CPU object and class structs
* - register the type for use with g_autoptr
* - provide three standard type cast functions
*
* The object struct and class struct need to be declared manually.
*/
#define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \
typedef struct ArchCPU CpuInstanceType; \
OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
typedef enum MMUAccessType {
MMU_DATA_LOAD = 0,
MMU_DATA_STORE = 1,
@ -351,7 +358,7 @@ struct CPUState {
AddressSpace *as;
MemoryRegion *memory;
void *env_ptr; /* CPUArchState */
CPUArchState *env_ptr;
IcountDecr *icount_decr_ptr;
/* Accessed in parallel; all accesses must be atomic */

2
include/qemu/typedefs.h
View File

@ -26,6 +26,7 @@ typedef struct AddressSpace AddressSpace;
typedef struct AioContext AioContext;
typedef struct Aml Aml;
typedef struct AnnounceTimer AnnounceTimer;
typedef struct ArchCPU ArchCPU;
typedef struct BdrvDirtyBitmap BdrvDirtyBitmap;
typedef struct BdrvDirtyBitmapIter BdrvDirtyBitmapIter;
typedef struct BlockBackend BlockBackend;
@ -39,6 +40,7 @@ typedef struct CompatProperty CompatProperty;
typedef struct CoMutex CoMutex;
typedef struct ConfidentialGuestSupport ConfidentialGuestSupport;
typedef struct CPUAddressSpace CPUAddressSpace;
typedef struct CPUArchState CPUArchState;
typedef struct CPUState CPUState;
typedef struct DeviceListener DeviceListener;
typedef struct DeviceState DeviceState;

3
include/sysemu/accel-ops.h
View File

@ -28,8 +28,11 @@ struct AccelOpsClass {
/* initialization function called when accel is chosen */
void (*ops_init)(AccelOpsClass *ops);
bool (*cpus_are_resettable)(void);
void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */
void (*kick_vcpu_thread)(CPUState *cpu);
bool (*cpu_thread_is_idle)(CPUState *cpu);
void (*synchronize_post_reset)(CPUState *cpu);
void (*synchronize_post_init)(CPUState *cpu);

2
include/sysemu/arch_init.h
View File

@ -28,4 +28,6 @@ enum {
extern const uint32_t arch_type;
void qemu_init_arch_modules(void);
#endif

18
include/sysemu/hax.h
View File

@ -25,17 +25,23 @@
int hax_sync_vcpus(void);
#ifdef NEED_CPU_H
# ifdef CONFIG_HAX
# define CONFIG_HAX_IS_POSSIBLE
# endif
#else /* !NEED_CPU_H */
# define CONFIG_HAX_IS_POSSIBLE
#endif
#ifdef CONFIG_HAX
#ifdef CONFIG_HAX_IS_POSSIBLE
int hax_enabled(void);
extern bool hax_allowed;
#else /* CONFIG_HAX */
#define hax_enabled() (hax_allowed)
#define hax_enabled() (0)
#else /* !CONFIG_HAX_IS_POSSIBLE */
#endif /* CONFIG_HAX */
#define hax_enabled() (0)
#endif /* NEED_CPU_H */
#endif /* CONFIG_HAX_IS_POSSIBLE */
#endif /* QEMU_HAX_H */

5
include/sysemu/hw_accel.h
View File

@ -23,9 +23,4 @@ void cpu_synchronize_post_reset(CPUState *cpu);
void cpu_synchronize_post_init(CPUState *cpu);
void cpu_synchronize_pre_loadvm(CPUState *cpu);
static inline bool cpu_check_are_resettable(void)
{
return kvm_enabled() ? kvm_cpu_check_are_resettable() : true;
}
#endif /* QEMU_HW_ACCEL_H */

6
include/sysemu/kvm.h
View File

@ -249,6 +249,9 @@ int kvm_has_intx_set_mask(void);
bool kvm_arm_supports_user_irq(void);
int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr);
int kvm_on_sigbus(int code, void *addr);
#ifdef NEED_CPU_H
#include "cpu.h"
@ -261,9 +264,6 @@ int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr,
void kvm_remove_all_breakpoints(CPUState *cpu);
int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap);
int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr);
int kvm_on_sigbus(int code, void *addr);
/* internal API */
int kvm_ioctl(KVMState *s, int type, ...);

5
include/sysemu/memory_mapping.h
View File

@ -15,8 +15,7 @@
#define MEMORY_MAPPING_H
#include "qemu/queue.h"
#include "exec/cpu-defs.h"
#include "exec/memory.h"
#include "exec/cpu-common.h"
typedef struct GuestPhysBlock {
/* visible to guest, reflects PCI hole, etc */
@ -43,7 +42,7 @@ typedef struct GuestPhysBlockList {
/* The physical and virtual address in the memory mapping are contiguous. */
typedef struct MemoryMapping {
hwaddr phys_addr;
target_ulong virt_addr;
vaddr virt_addr;
ram_addr_t length;
QTAILQ_ENTRY(MemoryMapping) next;
} MemoryMapping;

4
meson.build
View File

@ -2432,8 +2432,8 @@ if get_option('cfi') and slirp_opt == 'system'
endif
fdt = not_found
fdt_opt = get_option('fdt')
if have_system
fdt_opt = get_option('fdt')
if fdt_opt in ['enabled', 'auto', 'system']
have_internal = fs.exists(meson.current_source_dir() / 'dtc/libfdt/Makefile.libfdt')
fdt = cc.find_library('fdt', kwargs: static_kwargs,
@ -2476,6 +2476,8 @@ if have_system
fdt = declare_dependency(link_with: libfdt,
include_directories: fdt_inc)
endif
else
fdt_opt = 'disabled'
endif
if not fdt.found() and fdt_required.length() > 0
error('fdt not available but required by targets ' + ', '.join(fdt_required))

9
softmmu/arch_init.c
View File

@ -22,6 +22,7 @@
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "qemu/module.h"
#include "sysemu/arch_init.h"
#ifdef TARGET_SPARC
@ -39,3 +40,11 @@ int graphic_depth = 32;
#endif
const uint32_t arch_type = QEMU_ARCH;
void qemu_init_arch_modules(void)
{
#ifdef CONFIG_MODULES
module_init_info(qemu_modinfo);
module_allow_arch(TARGET_NAME);
#endif
}

1
softmmu/cpu-timers.c
View File

@ -28,7 +28,6 @@
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "exec/exec-all.h"
#include "sysemu/cpus.h"
#include "qemu/main-loop.h"
#include "qemu/option.h"

23
softmmu/cpus.c
View File

@ -33,7 +33,7 @@
#include "qapi/qmp/qerror.h"
#include "exec/gdbstub.h"
#include "sysemu/hw_accel.h"
#include "exec/exec-all.h"
#include "exec/cpu-common.h"
#include "qemu/thread.h"
#include "qemu/plugin.h"
#include "sysemu/cpus.h"
@ -67,6 +67,11 @@
static QemuMutex qemu_global_mutex;
/*
* The chosen accelerator is supposed to register this.
*/
static const AccelOpsClass *cpus_accel;
bool cpu_is_stopped(CPUState *cpu)
{
return cpu->stopped || !runstate_is_running();
@ -85,10 +90,12 @@ bool cpu_thread_is_idle(CPUState *cpu)
if (cpu_is_stopped(cpu)) {
return true;
}
if (!cpu->halted || cpu_has_work(cpu) ||
kvm_halt_in_kernel() || whpx_apic_in_platform()) {
if (!cpu->halted || cpu_has_work(cpu)) {
return false;
}
if (cpus_accel->cpu_thread_is_idle) {
return cpus_accel->cpu_thread_is_idle(cpu);
}
return true;
}
@ -122,11 +129,6 @@ void hw_error(const char *fmt, ...)
abort();
}
/*
* The chosen accelerator is supposed to register this.
*/
static const AccelOpsClass *cpus_accel;
void cpu_synchronize_all_states(void)
{
CPUState *cpu;
@ -193,7 +195,10 @@ void cpu_synchronize_pre_loadvm(CPUState *cpu)
bool cpus_are_resettable(void)
{
return cpu_check_are_resettable();
if (cpus_accel->cpus_are_resettable) {
return cpus_accel->cpus_are_resettable();
}
return true;
}
int64_t cpus_get_virtual_clock(void)

2
softmmu/globals.c
View File

@ -25,8 +25,6 @@
#include "qemu/osdep.h"
#include "exec/cpu-common.h"
#include "hw/display/vga.h"
#include "hw/i386/pc.h"
#include "hw/i386/x86.h"
#include "hw/loader.h"
#include "hw/xen/xen.h"
#include "net/net.h"

1
softmmu/memory_mapping.c
View File

@ -17,6 +17,7 @@
#include "sysemu/memory_mapping.h"
#include "exec/memory.h"
#include "exec/address-spaces.h"
#include "hw/core/cpu.h"
//#define DEBUG_GUEST_PHYS_REGION_ADD

24
softmmu/meson.build
View File

@ -1,20 +1,9 @@
specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: [files(
'arch_init.c',
'balloon.c',
'cpus.c',
'cpu-throttle.c',
'datadir.c',
'globals.c',
'physmem.c',
'ioport.c',
'rtc.c',
'runstate.c',
'memory.c',
'memory_mapping.c',
'physmem.c',
'qtest.c',
'vl.c',
'cpu-timers.c',
'runstate-action.c',
)])
specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: [files(
@ -22,9 +11,20 @@ specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: [files(
)])
softmmu_ss.add(files(
'balloon.c',
'bootdevice.c',
'cpus.c',
'cpu-throttle.c',
'cpu-timers.c',
'datadir.c',
'dma-helpers.c',
'globals.c',
'memory_mapping.c',
'qdev-monitor.c',
'rtc.c',
'runstate-action.c',
'runstate.c',
'vl.c',
), sdl, libpmem, libdaxctl)
if have_tpm

7
softmmu/physmem.c
View File

@ -61,7 +61,6 @@
#include "exec/memory-internal.h"
#include "exec/ram_addr.h"
#include "exec/log.h"
#include "qemu/pmem.h"
@ -3436,11 +3435,11 @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
#include "memory_ldst.c.inc"
/* virtual memory access for debug (includes writing to ROM) */
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
void *ptr, target_ulong len, bool is_write)
int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
void *ptr, size_t len, bool is_write)
{
hwaddr phys_addr;
target_ulong l, page;
vaddr l, page;
uint8_t *buf = ptr;
cpu_synchronize_state(cpu);

5
softmmu/vl.c
View File

@ -2815,10 +2815,7 @@ void qemu_init(int argc, char **argv, char **envp)
error_init(argv[0]);
qemu_init_exec_dir(argv[0]);
#ifdef CONFIG_MODULES
module_init_info(qemu_modinfo);
module_allow_arch(TARGET_NAME);
#endif
qemu_init_arch_modules();
qemu_init_subsystems();

3
target/alpha/cpu-qom.h
View File

@ -25,8 +25,7 @@
#define TYPE_ALPHA_CPU "alpha-cpu"
OBJECT_DECLARE_TYPE(AlphaCPU, AlphaCPUClass,
ALPHA_CPU)
OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
/**
* AlphaCPUClass:

11
target/alpha/cpu.h
View File

@ -197,9 +197,7 @@ enum {
#define MMU_USER_IDX 1
#define MMU_PHYS_IDX 2
typedef struct CPUAlphaState CPUAlphaState;
struct CPUAlphaState {
typedef struct CPUArchState {
uint64_t ir[31];
float64 fir[31];
uint64_t pc;
@ -251,7 +249,7 @@ struct CPUAlphaState {
uint32_t features;
uint32_t amask;
int implver;
};
} CPUAlphaState;
/**
* AlphaCPU:
@ -259,7 +257,7 @@ struct CPUAlphaState {
*
* An Alpha CPU.
*/
struct AlphaCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -285,9 +283,6 @@ int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#define cpu_list alpha_cpu_list
typedef CPUAlphaState CPUArchState;
typedef AlphaCPU ArchCPU;
#include "exec/cpu-all.h"
enum {

1
target/alpha/translate.c
View File

@ -20,7 +20,6 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "sysemu/cpus.h"
#include "sysemu/cpu-timers.h"
#include "disas/disas.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"

3
target/arm/cpu-qom.h
View File

@ -27,8 +27,7 @@ struct arm_boot_info;
#define TYPE_ARM_CPU "arm-cpu"
OBJECT_DECLARE_TYPE(ARMCPU, ARMCPUClass,
ARM_CPU)
OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU

7
target/arm/cpu.h
View File

@ -232,7 +232,7 @@ typedef struct CPUARMTBFlags {
target_ulong flags2;
} CPUARMTBFlags;
typedef struct CPUARMState {
typedef struct CPUArchState {
/* Regs for current mode. */
uint32_t regs[16];
@ -774,7 +774,7 @@ typedef struct ARMISARegisters ARMISARegisters;
*
* An ARM CPU core.
*/
struct ARMCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -3410,9 +3410,6 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
}
}
typedef CPUARMState CPUArchState;
typedef ARMCPU ArchCPU;
#include "exec/cpu-all.h"
/*

2
target/arm/hvf_arm.h
View File

@ -13,6 +13,6 @@
#include "cpu.h"
void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu);
void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu);
#endif

3
target/avr/cpu-qom.h
View File

@ -26,8 +26,7 @@
#define TYPE_AVR_CPU "avr-cpu"
OBJECT_DECLARE_TYPE(AVRCPU, AVRCPUClass,
AVR_CPU)
OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
/**
* AVRCPUClass:

13
target/avr/cpu.h
View File

@ -108,9 +108,7 @@ typedef enum AVRFeature {
AVR_FEATURE_RAMPZ,
} AVRFeature;
typedef struct CPUAVRState CPUAVRState;
struct CPUAVRState {
typedef struct CPUArchState {
uint32_t pc_w; /* 0x003fffff up to 22 bits */
uint32_t sregC; /* 0x00000001 1 bit */
@ -137,7 +135,7 @@ struct CPUAVRState {
bool fullacc; /* CPU/MEM if true MEM only otherwise */
uint64_t features;
};
} CPUAVRState;
/**
* AVRCPU:
@ -145,14 +143,14 @@ struct CPUAVRState {
*
* A AVR CPU.
*/
typedef struct AVRCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUAVRState env;
} AVRCPU;
};
extern const struct VMStateDescription vms_avr_cpu;
@ -247,9 +245,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
typedef CPUAVRState CPUArchState;
typedef AVRCPU ArchCPU;
#include "exec/cpu-all.h"
#endif /* !defined (QEMU_AVR_CPU_H) */

3
target/cris/cpu-qom.h
View File

@ -25,8 +25,7 @@
#define TYPE_CRIS_CPU "cris-cpu"
OBJECT_DECLARE_TYPE(CRISCPU, CRISCPUClass,
CRIS_CPU)
OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
/**
* CRISCPUClass:

7
target/cris/cpu.h
View File

@ -105,7 +105,7 @@ typedef struct {
uint32_t lo;
} TLBSet;
typedef struct CPUCRISState {
typedef struct CPUArchState {
uint32_t regs[16];
/* P0 - P15 are referred to as special registers in the docs. */
uint32_t pregs[16];
@ -173,7 +173,7 @@ typedef struct CPUCRISState {
*
* A CRIS CPU.
*/
struct CRISCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -265,9 +265,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
typedef CPUCRISState CPUArchState;
typedef CRISCPU ArchCPU;
#include "exec/cpu-all.h"
static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,

23
target/hexagon/cpu.h
View File

@ -1,5 +1,5 @@
/*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
* Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -18,14 +18,13 @@
#ifndef HEXAGON_CPU_H
#define HEXAGON_CPU_H
/* Forward declaration needed by some of the header files */
typedef struct CPUHexagonState CPUHexagonState;
#include "fpu/softfloat-types.h"
#include "exec/cpu-defs.h"
#include "hex_regs.h"
#include "mmvec/mmvec.h"
#include "qom/object.h"
#include "hw/core/cpu.h"
#define NUM_PREGS 4
#define TOTAL_PER_THREAD_REGS 64
@ -75,7 +74,7 @@ typedef struct {
/* Maximum number of vector temps in a packet */
#define VECTOR_TEMPS_MAX 4
struct CPUHexagonState {
typedef struct CPUArchState {
target_ulong gpr[TOTAL_PER_THREAD_REGS];
target_ulong pred[NUM_PREGS];
target_ulong branch_taken;
@ -129,14 +128,9 @@ struct CPUHexagonState {
target_ulong vstore_pending[VSTORES_MAX];
bool vtcm_pending;
VTCMStoreLog vtcm_log;
};
} CPUHexagonState;
#define HEXAGON_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(HexagonCPUClass, (klass), TYPE_HEXAGON_CPU)
#define HEXAGON_CPU(obj) \
OBJECT_CHECK(HexagonCPU, (obj), TYPE_HEXAGON_CPU)
#define HEXAGON_CPU_GET_CLASS(obj) \
OBJECT_GET_CLASS(HexagonCPUClass, (obj), TYPE_HEXAGON_CPU)
OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
typedef struct HexagonCPUClass {
/*< private >*/
@ -146,7 +140,7 @@ typedef struct HexagonCPUClass {
DeviceReset parent_reset;
} HexagonCPUClass;
typedef struct HexagonCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -155,7 +149,7 @@ typedef struct HexagonCPU {
bool lldb_compat;
target_ulong lldb_stack_adjust;
} HexagonCPU;
};
#include "cpu_bits.h"
@ -180,7 +174,6 @@ static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
#endif
}
typedef struct CPUHexagonState CPUArchState;
typedef HexagonCPU ArchCPU;
void hexagon_translate_init(void);

3
target/hppa/cpu-qom.h
View File

@ -25,8 +25,7 @@
#define TYPE_HPPA_CPU "hppa-cpu"
OBJECT_DECLARE_TYPE(HPPACPU, HPPACPUClass,
HPPA_CPU)
OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU)
/**
* HPPACPUClass:

12
target/hppa/cpu.h
View File

@ -138,8 +138,6 @@
#define CR_IPSW 22
#define CR_EIRR 23
typedef struct CPUHPPAState CPUHPPAState;
#if TARGET_REGISTER_BITS == 32
typedef uint32_t target_ureg;
typedef int32_t target_sreg;
@ -168,7 +166,7 @@ typedef struct {
unsigned access_id : 16;
} hppa_tlb_entry;
struct CPUHPPAState {
typedef struct CPUArchState {
target_ureg gr[32];
uint64_t fr[32];
uint64_t sr[8]; /* stored shifted into place for gva */
@ -207,7 +205,7 @@ struct CPUHPPAState {
/* ??? We should use a more intelligent data structure. */
hppa_tlb_entry tlb[HPPA_TLB_ENTRIES];
uint32_t tlb_last;
};
} CPUHPPAState;
/**
* HPPACPU:
@ -215,7 +213,7 @@ struct CPUHPPAState {
*
* An HPPA CPU.
*/
struct HPPACPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -225,10 +223,6 @@ struct HPPACPU {
QEMUTimer *alarm_timer;
};
typedef CPUHPPAState CPUArchState;
typedef HPPACPU ArchCPU;
#include "exec/cpu-all.h"
static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)

3
target/i386/cpu-qom.h
View File

@ -30,8 +30,7 @@
#define TYPE_X86_CPU "i386-cpu"
#endif
OBJECT_DECLARE_TYPE(X86CPU, X86CPUClass,
X86_CPU)
OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
typedef struct X86CPUModel X86CPUModel;

7
target/i386/cpu.h
View File

@ -1431,7 +1431,7 @@ typedef struct HVFX86LazyFlags {
target_ulong auxbits;
} HVFX86LazyFlags;
typedef struct CPUX86State {
typedef struct CPUArchState {
/* standard registers */
target_ulong regs[CPU_NB_REGS];
target_ulong eip;
@ -1707,7 +1707,7 @@ struct kvm_msrs;
*
* An x86 CPU.
*/
struct X86CPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -2074,9 +2074,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
#define CC_SRC2 (env->cc_src2)
#define CC_OP (env->cc_op)
typedef CPUX86State CPUArchState;
typedef X86CPU ArchCPU;
#include "exec/cpu-all.h"
#include "svm.h"

11
target/i386/hax/hax-all.c
View File

@ -49,18 +49,13 @@ const uint32_t hax_cur_version = 0x4; /* API v4: unmapping and MMIO moves */
/* Minimum HAX kernel version */
const uint32_t hax_min_version = 0x4; /* API v4: supports unmapping */
static bool hax_allowed;
bool hax_allowed;
struct hax_state hax_global;
static void hax_vcpu_sync_state(CPUArchState *env, int modified);
static int hax_arch_get_registers(CPUArchState *env);
int hax_enabled(void)
{
return hax_allowed;
}
int valid_hax_tunnel_size(uint16_t size)
{
return size >= sizeof(struct hax_tunnel);
@ -227,7 +222,7 @@ int hax_init_vcpu(CPUState *cpu)
cpu->hax_vcpu = hax_global.vm->vcpus[cpu->cpu_index];
cpu->vcpu_dirty = true;
qemu_register_reset(hax_reset_vcpu_state, (CPUArchState *) (cpu->env_ptr));
qemu_register_reset(hax_reset_vcpu_state, cpu->env_ptr);
return ret;
}
@ -674,7 +669,7 @@ void hax_cpu_synchronize_pre_loadvm(CPUState *cpu)
int hax_smp_cpu_exec(CPUState *cpu)
{
CPUArchState *env = (CPUArchState *) (cpu->env_ptr);
CPUArchState *env = cpu->env_ptr;
int fatal;
int ret;

110
target/i386/hvf/x86_emu.c
View File

@ -171,12 +171,12 @@ void write_val_to_reg(target_ulong reg_ptr, target_ulong val, int size)
}
}
static bool is_host_reg(struct CPUX86State *env, target_ulong ptr)
static bool is_host_reg(CPUX86State *env, target_ulong ptr)
{
return (ptr - (target_ulong)&env->regs[0]) < sizeof(env->regs);
}
void write_val_ext(struct CPUX86State *env, target_ulong ptr, target_ulong val, int size)
void write_val_ext(CPUX86State *env, target_ulong ptr, target_ulong val, int size)
{
if (is_host_reg(env, ptr)) {
write_val_to_reg(ptr, val, size);
@ -185,14 +185,14 @@ void write_val_ext(struct CPUX86State *env, target_ulong ptr, target_ulong val,
vmx_write_mem(env_cpu(env), ptr, &val, size);
}
uint8_t *read_mmio(struct CPUX86State *env, target_ulong ptr, int bytes)
uint8_t *read_mmio(CPUX86State *env, target_ulong ptr, int bytes)
{
vmx_read_mem(env_cpu(env), env->hvf_mmio_buf, ptr, bytes);
return env->hvf_mmio_buf;
}
target_ulong read_val_ext(struct CPUX86State *env, target_ulong ptr, int size)
target_ulong read_val_ext(CPUX86State *env, target_ulong ptr, int size)
{
target_ulong val;
uint8_t *mmio_ptr;
@ -222,7 +222,7 @@ target_ulong read_val_ext(struct CPUX86State *env, target_ulong ptr, int size)
return val;
}
static void fetch_operands(struct CPUX86State *env, struct x86_decode *decode,
static void fetch_operands(CPUX86State *env, struct x86_decode *decode,
int n, bool val_op0, bool val_op1, bool val_op2)
{
int i;
@ -261,7 +261,7 @@ static void fetch_operands(struct CPUX86State *env, struct x86_decode *decode,
}
}
static void exec_mov(struct CPUX86State *env, struct x86_decode *decode)
static void exec_mov(CPUX86State *env, struct x86_decode *decode)
{
fetch_operands(env, decode, 2, false, true, false);
write_val_ext(env, decode->op[0].ptr, decode->op[1].val,
@ -270,49 +270,49 @@ static void exec_mov(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
static void exec_add(struct CPUX86State *env, struct x86_decode *decode)
static void exec_add(CPUX86State *env, struct x86_decode *decode)
{
EXEC_2OP_FLAGS_CMD(env, decode, +, SET_FLAGS_OSZAPC_ADD, true);
env->eip += decode->len;
}
static void exec_or(struct CPUX86State *env, struct x86_decode *decode)
static void exec_or(CPUX86State *env, struct x86_decode *decode)
{
EXEC_2OP_FLAGS_CMD(env, decode, |, SET_FLAGS_OSZAPC_LOGIC, true);
env->eip += decode->len;
}
static void exec_adc(struct CPUX86State *env, struct x86_decode *decode)
static void exec_adc(CPUX86State *env, struct x86_decode *decode)
{
EXEC_2OP_FLAGS_CMD(env, decode, +get_CF(env)+, SET_FLAGS_OSZAPC_ADD, true);
env->eip += decode->len;
}
static void exec_sbb(struct CPUX86State *env, struct x86_decode *decode)
static void exec_sbb(CPUX86State *env, struct x86_decode *decode)
{
EXEC_2OP_FLAGS_CMD(env, decode, -get_CF(env)-, SET_FLAGS_OSZAPC_SUB, true);
env->eip += decode->len;
}
static void exec_and(struct CPUX86State *env, struct x86_decode *decode)
static void exec_and(CPUX86State *env, struct x86_decode *decode)
{
EXEC_2OP_FLAGS_CMD(env, decode, &, SET_FLAGS_OSZAPC_LOGIC, true);
env->eip += decode->len;
}
static void exec_sub(struct CPUX86State *env, struct x86_decode *decode)
static void exec_sub(CPUX86State *env, struct x86_decode *decode)
{
EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, true);
env->eip += decode->len;
}
static void exec_xor(struct CPUX86State *env, struct x86_decode *decode)
static void exec_xor(CPUX86State *env, struct x86_decode *decode)
{
EXEC_2OP_FLAGS_CMD(env, decode, ^, SET_FLAGS_OSZAPC_LOGIC, true);
env->eip += decode->len;
}
static void exec_neg(struct CPUX86State *env, struct x86_decode *decode)
static void exec_neg(CPUX86State *env, struct x86_decode *decode)
{
/*EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false);*/
int32_t val;
@ -335,13 +335,13 @@ static void exec_neg(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
static void exec_cmp(struct CPUX86State *env, struct x86_decode *decode)
static void exec_cmp(CPUX86State *env, struct x86_decode *decode)
{
EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false);
env->eip += decode->len;
}
static void exec_inc(struct CPUX86State *env, struct x86_decode *decode)
static void exec_inc(CPUX86State *env, struct x86_decode *decode)
{
decode->op[1].type = X86_VAR_IMMEDIATE;
decode->op[1].val = 0;
@ -351,7 +351,7 @@ static void exec_inc(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
static void exec_dec(struct CPUX86State *env, struct x86_decode *decode)
static void exec_dec(CPUX86State *env, struct x86_decode *decode)
{
decode->op[1].type = X86_VAR_IMMEDIATE;
decode->op[1].val = 0;
@ -360,13 +360,13 @@ static void exec_dec(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
static void exec_tst(struct CPUX86State *env, struct x86_decode *decode)
static void exec_tst(CPUX86State *env, struct x86_decode *decode)
{
EXEC_2OP_FLAGS_CMD(env, decode, &, SET_FLAGS_OSZAPC_LOGIC, false);
env->eip += decode->len;
}
static void exec_not(struct CPUX86State *env, struct x86_decode *decode)
static void exec_not(CPUX86State *env, struct x86_decode *decode)
{
fetch_operands(env, decode, 1, true, false, false);
@ -375,7 +375,7 @@ static void exec_not(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
void exec_movzx(struct CPUX86State *env, struct x86_decode *decode)
void exec_movzx(CPUX86State *env, struct x86_decode *decode)
{
int src_op_size;
int op_size = decode->operand_size;
@ -395,7 +395,7 @@ void exec_movzx(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
static void exec_out(struct CPUX86State *env, struct x86_decode *decode)
static void exec_out(CPUX86State *env, struct x86_decode *decode)
{
switch (decode->opcode[0]) {
case 0xe6:
@ -419,7 +419,7 @@ static void exec_out(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
static void exec_in(struct CPUX86State *env, struct x86_decode *decode)
static void exec_in(CPUX86State *env, struct x86_decode *decode)
{
target_ulong val = 0;
switch (decode->opcode[0]) {
@ -455,7 +455,7 @@ static void exec_in(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
static inline void string_increment_reg(struct CPUX86State *env, int reg,
static inline void string_increment_reg(CPUX86State *env, int reg,
struct x86_decode *decode)
{
target_ulong val = read_reg(env, reg, decode->addressing_size);
@ -467,8 +467,8 @@ static inline void string_increment_reg(struct CPUX86State *env, int reg,
write_reg(env, reg, val, decode->addressing_size);
}
static inline void string_rep(struct CPUX86State *env, struct x86_decode *decode,
void (*func)(struct CPUX86State *env,
static inline void string_rep(CPUX86State *env, struct x86_decode *decode,
void (*func)(CPUX86State *env,
struct x86_decode *ins), int rep)
{
target_ulong rcx = read_reg(env, R_ECX, decode->addressing_size);
@ -484,7 +484,7 @@ static inline void string_rep(struct CPUX86State *env, struct x86_decode *decode
}
}
static void exec_ins_single(struct CPUX86State *env, struct x86_decode *decode)
static void exec_ins_single(CPUX86State *env, struct x86_decode *decode)
{
target_ulong addr = linear_addr_size(env_cpu(env), RDI(env),
decode->addressing_size, R_ES);
@ -497,7 +497,7 @@ static void exec_ins_single(struct CPUX86State *env, struct x86_decode *decode)
string_increment_reg(env, R_EDI, decode);
}
static void exec_ins(struct CPUX86State *env, struct x86_decode *decode)
static void exec_ins(CPUX86State *env, struct x86_decode *decode)
{
if (decode->rep) {
string_rep(env, decode, exec_ins_single, 0);
@ -508,7 +508,7 @@ static void exec_ins(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
static void exec_outs_single(struct CPUX86State *env, struct x86_decode *decode)
static void exec_outs_single(CPUX86State *env, struct x86_decode *decode)
{
target_ulong addr = decode_linear_addr(env, decode, RSI(env), R_DS);
@ -520,7 +520,7 @@ static void exec_outs_single(struct CPUX86State *env, struct x86_decode *decode)
string_increment_reg(env, R_ESI, decode);
}
static void exec_outs(struct CPUX86State *env, struct x86_decode *decode)
static void exec_outs(CPUX86State *env, struct x86_decode *decode)
{
if (decode->rep) {
string_rep(env, decode, exec_outs_single, 0);
@ -531,7 +531,7 @@ static void exec_outs(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
static void exec_movs_single(struct CPUX86State *env, struct x86_decode *decode)
static void exec_movs_single(CPUX86State *env, struct x86_decode *decode)
{
target_ulong src_addr;
target_ulong dst_addr;
@ -548,7 +548,7 @@ static void exec_movs_single(struct CPUX86State *env, struct x86_decode *decode)
string_increment_reg(env, R_EDI, decode);
}
static void exec_movs(struct CPUX86State *env, struct x86_decode *decode)
static void exec_movs(CPUX86State *env, struct x86_decode *decode)
{
if (decode->rep) {
string_rep(env, decode, exec_movs_single, 0);
@ -559,7 +559,7 @@ static void exec_movs(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
static void exec_cmps_single(struct CPUX86State *env, struct x86_decode *decode)
static void exec_cmps_single(CPUX86State *env, struct x86_decode *decode)
{
target_ulong src_addr;
target_ulong dst_addr;
@ -579,7 +579,7 @@ static void exec_cmps_single(struct CPUX86State *env, struct x86_decode *decode)
string_increment_reg(env, R_EDI, decode);
}
static void exec_cmps(struct CPUX86State *env, struct x86_decode *decode)
static void exec_cmps(CPUX86State *env, struct x86_decode *decode)
{
if (decode->rep) {
string_rep(env, decode, exec_cmps_single, decode->rep);
@ -590,7 +590,7 @@ static void exec_cmps(struct CPUX86State *env, struct x86_decode *decode)
}
static void exec_stos_single(struct CPUX86State *env, struct x86_decode *decode)
static void exec_stos_single(CPUX86State *env, struct x86_decode *decode)
{
target_ulong addr;
target_ulong val;
@ -604,7 +604,7 @@ static void exec_stos_single(struct CPUX86State *env, struct x86_decode *decode)
}
static void exec_stos(struct CPUX86State *env, struct x86_decode *decode)
static void exec_stos(CPUX86State *env, struct x86_decode *decode)
{
if (decode->rep) {
string_rep(env, decode, exec_stos_single, 0);
@ -615,7 +615,7 @@ static void exec_stos(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
static void exec_scas_single(struct CPUX86State *env, struct x86_decode *decode)
static void exec_scas_single(CPUX86State *env, struct x86_decode *decode)
{
target_ulong addr;
@ -628,7 +628,7 @@ static void exec_scas_single(struct CPUX86State *env, struct x86_decode *decode)
string_increment_reg(env, R_EDI, decode);
}
static void exec_scas(struct CPUX86State *env, struct x86_decode *decode)
static void exec_scas(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = R_EAX;
@ -641,7 +641,7 @@ static void exec_scas(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
static void exec_lods_single(struct CPUX86State *env, struct x86_decode *decode)
static void exec_lods_single(CPUX86State *env, struct x86_decode *decode)
{
target_ulong addr;
target_ulong val = 0;
@ -653,7 +653,7 @@ static void exec_lods_single(struct CPUX86State *env, struct x86_decode *decode)
string_increment_reg(env, R_ESI, decode);
}
static void exec_lods(struct CPUX86State *env, struct x86_decode *decode)
static void exec_lods(CPUX86State *env, struct x86_decode *decode)
{
if (decode->rep) {
string_rep(env, decode, exec_lods_single, 0);
@ -760,7 +760,7 @@ void simulate_rdmsr(struct CPUState *cpu)
RDX(env) = (uint32_t)(val >> 32);
}
static void exec_rdmsr(struct CPUX86State *env, struct x86_decode *decode)
static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode)
{
simulate_rdmsr(env_cpu(env));
env->eip += decode->len;
@ -855,7 +855,7 @@ void simulate_wrmsr(struct CPUState *cpu)
printf("write msr %llx\n", RCX(cpu));*/
}
static void exec_wrmsr(struct CPUX86State *env, struct x86_decode *decode)
static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode)
{
simulate_wrmsr(env_cpu(env));
env->eip += decode->len;
@ -865,7 +865,7 @@ static void exec_wrmsr(struct CPUX86State *env, struct x86_decode *decode)
* flag:
* 0 - bt, 1 - btc, 2 - bts, 3 - btr
*/
static void do_bt(struct CPUX86State *env, struct x86_decode *decode, int flag)
static void do_bt(CPUX86State *env, struct x86_decode *decode, int flag)
{
int32_t displacement;
uint8_t index;
@ -911,31 +911,31 @@ static void do_bt(struct CPUX86State *env, struct x86_decode *decode, int flag)
set_CF(env, cf);
}
static void exec_bt(struct CPUX86State *env, struct x86_decode *decode)
static void exec_bt(CPUX86State *env, struct x86_decode *decode)
{
do_bt(env, decode, 0);
env->eip += decode->len;
}
static void exec_btc(struct CPUX86State *env, struct x86_decode *decode)
static void exec_btc(CPUX86State *env, struct x86_decode *decode)
{
do_bt(env, decode, 1);
env->eip += decode->len;
}
static void exec_btr(struct CPUX86State *env, struct x86_decode *decode)
static void exec_btr(CPUX86State *env, struct x86_decode *decode)
{
do_bt(env, decode, 3);
env->eip += decode->len;
}
static void exec_bts(struct CPUX86State *env, struct x86_decode *decode)
static void exec_bts(CPUX86State *env, struct x86_decode *decode)
{
do_bt(env, decode, 2);
env->eip += decode->len;
}
void exec_shl(struct CPUX86State *env, struct x86_decode *decode)
void exec_shl(CPUX86State *env, struct x86_decode *decode)
{
uint8_t count;
int of = 0, cf = 0;
@ -1022,7 +1022,7 @@ void exec_movsx(CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
void exec_ror(struct CPUX86State *env, struct x86_decode *decode)
void exec_ror(CPUX86State *env, struct x86_decode *decode)
{
uint8_t count;
@ -1100,7 +1100,7 @@ void exec_ror(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
void exec_rol(struct CPUX86State *env, struct x86_decode *decode)
void exec_rol(CPUX86State *env, struct x86_decode *decode)
{
uint8_t count;
@ -1182,7 +1182,7 @@ void exec_rol(struct CPUX86State *env, struct x86_decode *decode)
}
void exec_rcl(struct CPUX86State *env, struct x86_decode *decode)
void exec_rcl(CPUX86State *env, struct x86_decode *decode)
{
uint8_t count;
int of = 0, cf = 0;
@ -1267,7 +1267,7 @@ void exec_rcl(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
void exec_rcr(struct CPUX86State *env, struct x86_decode *decode)
void exec_rcr(CPUX86State *env, struct x86_decode *decode)
{
uint8_t count;
int of = 0, cf = 0;
@ -1342,7 +1342,7 @@ void exec_rcr(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
static void exec_xchg(struct CPUX86State *env, struct x86_decode *decode)
static void exec_xchg(CPUX86State *env, struct x86_decode *decode)
{
fetch_operands(env, decode, 2, true, true, false);
@ -1354,7 +1354,7 @@ static void exec_xchg(struct CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
static void exec_xadd(struct CPUX86State *env, struct x86_decode *decode)
static void exec_xadd(CPUX86State *env, struct x86_decode *decode)
{
EXEC_2OP_FLAGS_CMD(env, decode, +, SET_FLAGS_OSZAPC_ADD, true);
write_val_ext(env, decode->op[1].ptr, decode->op[0].val,
@ -1365,7 +1365,7 @@ static void exec_xadd(struct CPUX86State *env, struct x86_decode *decode)
static struct cmd_handler {
enum x86_decode_cmd cmd;
void (*handler)(struct CPUX86State *env, struct x86_decode *ins);
void (*handler)(CPUX86State *env, struct x86_decode *ins);
} handlers[] = {
{X86_DECODE_CMD_INVL, NULL,},
{X86_DECODE_CMD_MOV, exec_mov},
@ -1465,7 +1465,7 @@ void store_regs(struct CPUState *cpu)
macvm_set_rip(cpu, env->eip);
}
bool exec_instruction(struct CPUX86State *env, struct x86_decode *ins)
bool exec_instruction(CPUX86State *env, struct x86_decode *ins)
{
/*if (hvf_vcpu_id(cpu))
printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), env->eip,

22
target/i386/hvf/x86_emu.h
View File

@ -24,7 +24,7 @@
#include "cpu.h"
void init_emu(void);
bool exec_instruction(struct CPUX86State *env, struct x86_decode *ins);
bool exec_instruction(CPUX86State *env, struct x86_decode *ins);
void load_regs(struct CPUState *cpu);
void store_regs(struct CPUState *cpu);
@ -36,15 +36,15 @@ target_ulong read_reg(CPUX86State *env, int reg, int size);
void write_reg(CPUX86State *env, int reg, target_ulong val, int size);
target_ulong read_val_from_reg(target_ulong reg_ptr, int size);
void write_val_to_reg(target_ulong reg_ptr, target_ulong val, int size);
void write_val_ext(struct CPUX86State *env, target_ulong ptr, target_ulong val, int size);
uint8_t *read_mmio(struct CPUX86State *env, target_ulong ptr, int bytes);
target_ulong read_val_ext(struct CPUX86State *env, target_ulong ptr, int size);
void write_val_ext(CPUX86State *env, target_ulong ptr, target_ulong val, int size);
uint8_t *read_mmio(CPUX86State *env, target_ulong ptr, int bytes);
target_ulong read_val_ext(CPUX86State *env, target_ulong ptr, int size);
void exec_movzx(struct CPUX86State *env, struct x86_decode *decode);
void exec_shl(struct CPUX86State *env, struct x86_decode *decode);
void exec_movsx(struct CPUX86State *env, struct x86_decode *decode);
void exec_ror(struct CPUX86State *env, struct x86_decode *decode);
void exec_rol(struct CPUX86State *env, struct x86_decode *decode);
void exec_rcl(struct CPUX86State *env, struct x86_decode *decode);
void exec_rcr(struct CPUX86State *env, struct x86_decode *decode);
void exec_movzx(CPUX86State *env, struct x86_decode *decode);
void exec_shl(CPUX86State *env, struct x86_decode *decode);
void exec_movsx(CPUX86State *env, struct x86_decode *decode);
void exec_ror(CPUX86State *env, struct x86_decode *decode);
void exec_rol(CPUX86State *env, struct x86_decode *decode);
void exec_rcl(CPUX86State *env, struct x86_decode *decode);
void exec_rcr(CPUX86State *env, struct x86_decode *decode);
#endif

14
target/i386/nvmm/nvmm-all.c
View File

@ -85,7 +85,7 @@ nvmm_set_segment(struct nvmm_x64_state_seg *nseg, const SegmentCache *qseg)
static void
nvmm_set_registers(CPUState *cpu)
{
struct CPUX86State *env = (CPUArchState *)cpu->env_ptr;
CPUX86State *env = cpu->env_ptr;
struct nvmm_machine *mach = get_nvmm_mach();
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
@ -222,7 +222,7 @@ nvmm_get_segment(SegmentCache *qseg, const struct nvmm_x64_state_seg *nseg)
static void
nvmm_get_registers(CPUState *cpu)
{
struct CPUX86State *env = (CPUArchState *)cpu->env_ptr;
CPUX86State *env = cpu->env_ptr;
struct nvmm_machine *mach = get_nvmm_mach();
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
@ -347,7 +347,7 @@ nvmm_get_registers(CPUState *cpu)
static bool
nvmm_can_take_int(CPUState *cpu)
{
struct CPUX86State *env = (CPUArchState *)cpu->env_ptr;
CPUX86State *env = cpu->env_ptr;
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
struct nvmm_machine *mach = get_nvmm_mach();
@ -394,7 +394,7 @@ nvmm_can_take_nmi(CPUState *cpu)
static void
nvmm_vcpu_pre_run(CPUState *cpu)
{
struct CPUX86State *env = (CPUArchState *)cpu->env_ptr;
CPUX86State *env = cpu->env_ptr;
struct nvmm_machine *mach = get_nvmm_mach();
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
@ -480,7 +480,7 @@ static void
nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit)
{
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
struct CPUX86State *env = (CPUArchState *)cpu->env_ptr;
CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
uint64_t tpr;
@ -652,7 +652,7 @@ static int
nvmm_handle_halted(struct nvmm_machine *mach, CPUState *cpu,
struct nvmm_vcpu_exit *exit)
{
struct CPUX86State *env = (CPUArchState *)cpu->env_ptr;
CPUX86State *env = cpu->env_ptr;
int ret = 0;
qemu_mutex_lock_iothread();
@ -685,7 +685,7 @@ nvmm_inject_ud(struct nvmm_machine *mach, struct nvmm_vcpu *vcpu)
static int
nvmm_vcpu_loop(CPUState *cpu)
{
struct CPUX86State *env = (CPUArchState *)cpu->env_ptr;
CPUX86State *env = cpu->env_ptr;
struct nvmm_machine *mach = get_nvmm_mach();
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
struct nvmm_vcpu *vcpu = &qcpu->vcpu;

1
target/i386/tcg/sysemu/excp_helper.c
View File

@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg/helper-tcg.h"
int get_pg_mode(CPUX86State *env)

1
target/i386/tcg/sysemu/misc_helper.c
View File

@ -23,6 +23,7 @@
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
#include "exec/address-spaces.h"
#include "exec/exec-all.h"
#include "tcg/helper-tcg.h"
void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)

6
target/i386/whpx/whpx-accel-ops.c
View File

@ -83,12 +83,18 @@ static void whpx_kick_vcpu_thread(CPUState *cpu)
}
}
static bool whpx_vcpu_thread_is_idle(CPUState *cpu)
{
return !whpx_apic_in_platform();
}
static void whpx_accel_ops_class_init(ObjectClass *oc, void *data)
{
AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
ops->create_vcpu_thread = whpx_start_vcpu_thread;
ops->kick_vcpu_thread = whpx_kick_vcpu_thread;
ops->cpu_thread_is_idle = whpx_vcpu_thread_is_idle;
ops->synchronize_post_reset = whpx_cpu_synchronize_post_reset;
ops->synchronize_post_init = whpx_cpu_synchronize_post_init;

18
target/i386/whpx/whpx-all.c
View File

@ -221,7 +221,7 @@ static SegmentCache whpx_seg_h2q(const WHV_X64_SEGMENT_REGISTER *hs)
static int whpx_set_tsc(CPUState *cpu)
{
struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr);
CPUX86State *env = cpu->env_ptr;
WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc;
WHV_REGISTER_VALUE tsc_val;
HRESULT hr;
@ -260,7 +260,7 @@ static void whpx_set_registers(CPUState *cpu, int level)
{
struct whpx_state *whpx = &whpx_global;
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr);
CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
struct whpx_register_set vcxt;
HRESULT hr;
@ -428,7 +428,7 @@ static void whpx_set_registers(CPUState *cpu, int level)
static int whpx_get_tsc(CPUState *cpu)
{
struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr);
CPUX86State *env = cpu->env_ptr;
WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc;
WHV_REGISTER_VALUE tsc_val;
HRESULT hr;
@ -449,7 +449,7 @@ static void whpx_get_registers(CPUState *cpu)
{
struct whpx_state *whpx = &whpx_global;
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr);
CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
struct whpx_register_set vcxt;
uint64_t tpr, apic_base;
@ -760,7 +760,7 @@ static int whpx_handle_portio(CPUState *cpu,
static int whpx_handle_halt(CPUState *cpu)
{
struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr);
CPUX86State *env = cpu->env_ptr;
int ret = 0;
qemu_mutex_lock_iothread();
@ -781,7 +781,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)
HRESULT hr;
struct whpx_state *whpx = &whpx_global;
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr);
CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
int irq;
uint8_t tpr;
@ -903,7 +903,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)
static void whpx_vcpu_post_run(CPUState *cpu)
{
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr);
CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
env->eflags = vcpu->exit_ctx.VpContext.Rflags;
@ -927,7 +927,7 @@ static void whpx_vcpu_post_run(CPUState *cpu)
static void whpx_vcpu_process_async_events(CPUState *cpu)
{
struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr);
CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
@ -1333,7 +1333,7 @@ int whpx_init_vcpu(CPUState *cpu)
struct whpx_state *whpx = &whpx_global;
struct whpx_vcpu *vcpu = NULL;
Error *local_error = NULL;
struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr);
CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
UINT64 freq = 0;
int ret;

3
target/m68k/cpu-qom.h
View File

@ -25,8 +25,7 @@
#define TYPE_M68K_CPU "m68k-cpu"
OBJECT_DECLARE_TYPE(M68kCPU, M68kCPUClass,
M68K_CPU)
OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
/*
* M68kCPUClass:

7
target/m68k/cpu.h
View File

@ -79,7 +79,7 @@
typedef CPU_LDoubleU FPReg;
typedef struct CPUM68KState {
typedef struct CPUArchState {
uint32_t dregs[8];
uint32_t aregs[8];
uint32_t pc;
@ -156,7 +156,7 @@ typedef struct CPUM68KState {
*
* A Motorola 68k CPU.
*/
struct M68kCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -574,9 +574,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
typedef CPUM68KState CPUArchState;
typedef M68kCPU ArchCPU;
#include "exec/cpu-all.h"
/* TB flags */

3
target/microblaze/cpu-qom.h
View File

@ -25,8 +25,7 @@
#define TYPE_MICROBLAZE_CPU "microblaze-cpu"
OBJECT_DECLARE_TYPE(MicroBlazeCPU, MicroBlazeCPUClass,
MICROBLAZE_CPU)
OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
/**
* MicroBlazeCPUClass:

9
target/microblaze/cpu.h
View File

@ -24,7 +24,7 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
typedef struct CPUMBState CPUMBState;
typedef struct CPUArchState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
#endif
@ -239,7 +239,7 @@ typedef struct CPUMBState CPUMBState;
#define USE_NON_SECURE_M_AXI_DC_MASK 0x4
#define USE_NON_SECURE_M_AXI_IC_MASK 0x8
struct CPUMBState {
struct CPUArchState {
uint32_t bvalue; /* TCG temporary, only valid during a TB */
uint32_t btarget; /* Full resolved branch destination */
@ -339,7 +339,7 @@ typedef struct {
*
* A MicroBlaze CPU.
*/
struct MicroBlazeCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
@ -394,9 +394,6 @@ void mb_tcg_init(void);
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
typedef CPUMBState CPUArchState;
typedef MicroBlazeCPU ArchCPU;
#include "exec/cpu-all.h"
/* Ensure there is no overlap between the two masks. */

2
target/microblaze/mmu.h
View File

@ -20,6 +20,8 @@
#ifndef TARGET_MICROBLAZE_MMU_H
#define TARGET_MICROBLAZE_MMU_H
#include "cpu.h"
#define MMU_R_PID 0
#define MMU_R_ZPR 1
#define MMU_R_TLBX 2

3
target/mips/cpu-qom.h
View File

@ -29,8 +29,7 @@
#define TYPE_MIPS_CPU "mips-cpu"
#endif
OBJECT_DECLARE_TYPE(MIPSCPU, MIPSCPUClass,
MIPS_CPU)
OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
/**
* MIPSCPUClass:

10
target/mips/cpu.h
View File

@ -524,8 +524,7 @@ struct TCState {
};
struct MIPSITUState;
typedef struct CPUMIPSState CPUMIPSState;
struct CPUMIPSState {
typedef struct CPUArchState {
TCState active_tc;
CPUMIPSFPUContext active_fpu;
@ -1161,7 +1160,7 @@ struct CPUMIPSState {
QEMUTimer *timer; /* Internal timer */
target_ulong exception_base; /* ExceptionBase input to the core */
uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */
};
} CPUMIPSState;
/**
* MIPSCPU:
@ -1172,7 +1171,7 @@ struct CPUMIPSState {
*
* A MIPS CPU.
*/
struct MIPSCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -1218,9 +1217,6 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
return hflags_mmu_index(env->hflags);
}
typedef CPUMIPSState CPUArchState;
typedef MIPSCPU ArchCPU;
#include "exec/cpu-all.h"
/* Exceptions */

15
target/mips/internal.h
View File

@ -12,6 +12,7 @@
#ifdef CONFIG_TCG
#include "tcg/tcg-internal.h"
#endif
#include "cpu.h"
/*
* MMU types, the first four entries have the same layout as the
@ -133,14 +134,14 @@ struct r4k_tlb_t {
struct CPUMIPSTLBContext {
uint32_t nb_tlb;
uint32_t tlb_in_use;
int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
int (*map_address)(CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, MMUAccessType access_type);
void (*helper_tlbwi)(struct CPUMIPSState *env);
void (*helper_tlbwr)(struct CPUMIPSState *env);
void (*helper_tlbp)(struct CPUMIPSState *env);
void (*helper_tlbr)(struct CPUMIPSState *env);
void (*helper_tlbinv)(struct CPUMIPSState *env);
void (*helper_tlbinvf)(struct CPUMIPSState *env);
void (*helper_tlbwi)(CPUMIPSState *env);
void (*helper_tlbwr)(CPUMIPSState *env);
void (*helper_tlbp)(CPUMIPSState *env);
void (*helper_tlbr)(CPUMIPSState *env);
void (*helper_tlbinv)(CPUMIPSState *env);
void (*helper_tlbinvf)(CPUMIPSState *env);
union {
struct {
r4k_tlb_t tlb[MIPS_TLB_MAX];

9
target/nios2/cpu.h
View File

@ -25,15 +25,14 @@
#include "hw/core/cpu.h"
#include "qom/object.h"
typedef struct CPUNios2State CPUNios2State;
typedef struct CPUArchState CPUNios2State;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
#endif
#define TYPE_NIOS2_CPU "nios2-cpu"
OBJECT_DECLARE_TYPE(Nios2CPU, Nios2CPUClass,
NIOS2_CPU)
OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
/**
* Nios2CPUClass:
@ -155,7 +154,7 @@ struct Nios2CPUClass {
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
struct CPUNios2State {
struct CPUArchState {
uint32_t regs[NUM_CORE_REGS];
#if !defined(CONFIG_USER_ONLY)
@ -170,7 +169,7 @@ struct CPUNios2State {
*
* A Nios2 CPU.
*/
struct Nios2CPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/

2
target/nios2/mmu.h
View File

@ -21,6 +21,8 @@
#ifndef NIOS2_MMU_H
#define NIOS2_MMU_H
#include "cpu.h"
typedef struct Nios2TLBEntry {
target_ulong tag;
target_ulong data;

17
target/openrisc/cpu.h
View File

@ -24,13 +24,9 @@
#include "hw/core/cpu.h"
#include "qom/object.h"
/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
struct OpenRISCCPU;
#define TYPE_OPENRISC_CPU "or1k-cpu"
OBJECT_DECLARE_TYPE(OpenRISCCPU, OpenRISCCPUClass,
OPENRISC_CPU)
OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
/**
* OpenRISCCPUClass:
@ -231,18 +227,18 @@ typedef struct CPUOpenRISCTLBContext {
OpenRISCTLBEntry itlb[TLB_SIZE];
OpenRISCTLBEntry dtlb[TLB_SIZE];
int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
int (*cpu_openrisc_map_address_code)(OpenRISCCPU *cpu,
hwaddr *physical,
int *prot,
target_ulong address, int rw);
int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
int (*cpu_openrisc_map_address_data)(OpenRISCCPU *cpu,
hwaddr *physical,
int *prot,
target_ulong address, int rw);
} CPUOpenRISCTLBContext;
#endif
typedef struct CPUOpenRISCState {
typedef struct CPUArchState {
target_ulong shadow_gpr[16][32]; /* Shadow registers */
target_ulong pc; /* Program counter */
@ -301,7 +297,7 @@ typedef struct CPUOpenRISCState {
*
* A OpenRISC CPU.
*/
struct OpenRISCCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -348,9 +344,6 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
typedef CPUOpenRISCState CPUArchState;
typedef OpenRISCCPU ArchCPU;
#include "exec/cpu-all.h"
#define TB_FLAGS_SM SR_SM

5
target/ppc/cpu-qom.h
View File

@ -29,10 +29,9 @@
#define TYPE_POWERPC_CPU "powerpc-cpu"
#endif
OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass,
POWERPC_CPU)
OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU)
typedef struct CPUPPCState CPUPPCState;
typedef struct CPUArchState CPUPPCState;
typedef struct ppc_tb_t ppc_tb_t;
typedef struct ppc_dcr_t ppc_dcr_t;

7
target/ppc/cpu.h
View File

@ -1077,7 +1077,7 @@ struct ppc_radix_page_info {
#define PPC_CPU_OPCODES_LEN 0x40
#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
struct CPUPPCState {
struct CPUArchState {
/* Most commonly used resources during translated code execution first */
target_ulong gpr[32]; /* general purpose registers */
target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
@ -1275,7 +1275,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
*
* A PowerPC CPU.
*/
struct PowerPCCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -1477,9 +1477,6 @@ void ppc_compat_add_property(Object *obj, const char *name,
uint32_t *compat_pvr, const char *basedesc);
#endif /* defined(TARGET_PPC64) */
typedef CPUPPCState CPUArchState;
typedef PowerPCCPU ArchCPU;
#include "exec/cpu-all.h"
/*****************************************************************************/

11
target/riscv/cpu.h
View File

@ -98,7 +98,7 @@ enum {
#define MAX_RISCV_PMPS (16)
typedef struct CPURISCVState CPURISCVState;
typedef struct CPUArchState CPURISCVState;
#if !defined(CONFIG_USER_ONLY)
#include "pmp.h"
@ -113,7 +113,7 @@ FIELD(VTYPE, VMA, 7, 1)
FIELD(VTYPE, VEDIV, 8, 2)
FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
struct CPURISCVState {
struct CPUArchState {
target_ulong gpr[32];
target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
uint64_t fpr[32]; /* assume both F and D extensions */
@ -320,8 +320,7 @@ struct CPURISCVState {
uint64_t kvm_timer_frequency;
};
OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
RISCV_CPU)
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
/**
* RISCVCPUClass:
@ -395,7 +394,7 @@ typedef struct RISCVCPUConfig RISCVCPUConfig;
*
* A RISCV CPU.
*/
struct RISCVCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -499,8 +498,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
typedef CPURISCVState CPUArchState;
typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, MEM_IDX, 0, 3)

1
target/riscv/csr.c
View File

@ -23,6 +23,7 @@
#include "cpu.h"
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
#include "sysemu/cpu-timers.h"
/* CSR function table public API */
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)

2
target/riscv/pmp.h
View File

@ -22,6 +22,8 @@
#ifndef RISCV_PMP_H
#define RISCV_PMP_H
#include "cpu.h"
typedef enum {
PMP_READ = 1 << 0,
PMP_WRITE = 1 << 1,

5
target/rx/cpu-qom.h
View File

@ -26,8 +26,7 @@
#define TYPE_RX62N_CPU RX_CPU_TYPE_NAME("rx62n")
OBJECT_DECLARE_TYPE(RXCPU, RXCPUClass,
RX_CPU)
OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
/*
* RXCPUClass:
@ -45,6 +44,4 @@ struct RXCPUClass {
DeviceReset parent_reset;
};
#define CPUArchState struct CPURXState
#endif

6
target/rx/cpu.h
View File

@ -65,7 +65,7 @@ enum {
NUM_REGS = 16,
};
typedef struct CPURXState {
typedef struct CPUArchState {
/* CPU registers */
uint32_t regs[NUM_REGS]; /* general registers */
uint32_t psw_o; /* O bit of status register */
@ -105,7 +105,7 @@ typedef struct CPURXState {
*
* A RX CPU
*/
struct RXCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -114,8 +114,6 @@ struct RXCPU {
CPURXState env;
};
typedef RXCPU ArchCPU;
#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_RX_CPU

7
target/s390x/cpu-qom.h
View File

@ -25,12 +25,13 @@
#define TYPE_S390_CPU "s390x-cpu"
OBJECT_DECLARE_TYPE(S390CPU, S390CPUClass,
S390_CPU)
OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU)
typedef struct S390CPUModel S390CPUModel;
typedef struct S390CPUDef S390CPUDef;
typedef struct CPUArchState CPUS390XState;
typedef enum cpu_reset_type {
S390_CPU_RESET_NORMAL,
S390_CPU_RESET_INITIAL,
@ -63,6 +64,4 @@ struct S390CPUClass {
void (*reset)(CPUState *cpu, cpu_reset_type type);
};
typedef struct CPUS390XState CPUS390XState;
#endif

7
target/s390x/cpu.h
View File

@ -51,7 +51,7 @@ typedef struct PSW {
uint64_t addr;
} PSW;
struct CPUS390XState {
struct CPUArchState {
uint64_t regs[16]; /* GP registers */
/*
* The floating point registers are part of the vector registers.
@ -163,7 +163,7 @@ static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
*
* An S/390 CPU.
*/
struct S390CPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -840,9 +840,6 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env);
/* outside of target/s390x/ */
S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
typedef CPUS390XState CPUArchState;
typedef S390CPU ArchCPU;
#include "exec/cpu-all.h"
#endif

3
target/sh4/cpu-qom.h
View File

@ -29,8 +29,7 @@
#define TYPE_SH7751R_CPU SUPERH_CPU_TYPE_NAME("sh7751r")
#define TYPE_SH7785_CPU SUPERH_CPU_TYPE_NAME("sh7785")
OBJECT_DECLARE_TYPE(SuperHCPU, SuperHCPUClass,
SUPERH_CPU)
OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
/**
* SuperHCPUClass:

7
target/sh4/cpu.h
View File

@ -130,7 +130,7 @@ typedef struct memory_content {
struct memory_content *next;
} memory_content;
typedef struct CPUSH4State {
typedef struct CPUArchState {
uint32_t flags; /* general execution flags */
uint32_t gregs[24]; /* general registers */
float32 fregs[32]; /* floating point registers */
@ -195,7 +195,7 @@ typedef struct CPUSH4State {
*
* A SuperH CPU.
*/
struct SuperHCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -264,9 +264,6 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
}
}
typedef CPUSH4State CPUArchState;
typedef SuperHCPU ArchCPU;
#include "exec/cpu-all.h"
/* MMU control register */

3
target/sparc/cpu-qom.h
View File

@ -29,8 +29,7 @@
#define TYPE_SPARC_CPU "sparc-cpu"
#endif
OBJECT_DECLARE_TYPE(SPARCCPU, SPARCCPUClass,
SPARC_CPU)
OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
typedef struct sparc_def_t sparc_def_t;
/**

9
target/sparc/cpu.h
View File

@ -420,7 +420,7 @@ struct CPUTimer
typedef struct CPUTimer CPUTimer;
typedef struct CPUSPARCState CPUSPARCState;
typedef struct CPUArchState CPUSPARCState;
#if defined(TARGET_SPARC64)
typedef union {
uint64_t mmuregs[16];
@ -439,7 +439,7 @@ typedef union {
};
} SparcV9MMU;
#endif
struct CPUSPARCState {
struct CPUArchState {
target_ulong gregs[8]; /* general registers */
target_ulong *regwptr; /* pointer to current register window */
target_ulong pc; /* program counter */
@ -556,7 +556,7 @@ struct CPUSPARCState {
*
* A SPARC CPU.
*/
struct SPARCCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -743,9 +743,6 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
#endif
}
typedef CPUSPARCState CPUArchState;
typedef SPARCCPU ArchCPU;
#include "exec/cpu-all.h"
#ifdef TARGET_SPARC64

3
target/tricore/cpu-qom.h
View File

@ -24,8 +24,7 @@
#define TYPE_TRICORE_CPU "tricore-cpu"
OBJECT_DECLARE_TYPE(TriCoreCPU, TriCoreCPUClass,
TRICORE_CPU)
OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)
struct TriCoreCPUClass {
/*< private >*/

10
target/tricore/cpu.h
View File

@ -28,8 +28,7 @@ struct tricore_boot_info;
typedef struct tricore_def_t tricore_def_t;
typedef struct CPUTriCoreState CPUTriCoreState;
struct CPUTriCoreState {
typedef struct CPUArchState {
/* GPR Register */
uint32_t gpr_a[16];
uint32_t gpr_d[16];
@ -189,7 +188,7 @@ struct CPUTriCoreState {
const tricore_def_t *cpu_model;
void *irq[8];
struct QEMUTimer *timer; /* Internal timer */
};
} CPUTriCoreState;
/**
* TriCoreCPU:
@ -197,7 +196,7 @@ struct CPUTriCoreState {
*
* A TriCore CPU.
*/
struct TriCoreCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -369,9 +368,6 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
return 0;
}
typedef CPUTriCoreState CPUArchState;
typedef TriCoreCPU ArchCPU;
#include "exec/cpu-all.h"
void cpu_state_reset(CPUTriCoreState *s);

3
target/xtensa/cpu-qom.h
View File

@ -34,8 +34,7 @@
#define TYPE_XTENSA_CPU "xtensa-cpu"
OBJECT_DECLARE_TYPE(XtensaCPU, XtensaCPUClass,
XTENSA_CPU)
OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU)
typedef struct XtensaConfig XtensaConfig;

13
target/xtensa/cpu.h
View File

@ -306,7 +306,7 @@ typedef enum {
INTTYPE_MAX
} interrupt_type;
struct CPUXtensaState;
typedef struct CPUArchState CPUXtensaState;
typedef struct xtensa_tlb_entry {
uint32_t vaddr;
@ -344,7 +344,7 @@ typedef struct XtensaGdbRegmap {
} XtensaGdbRegmap;
typedef struct XtensaCcompareTimer {
struct CPUXtensaState *env;
CPUXtensaState *env;
QEMUTimer *timer;
} XtensaCcompareTimer;
@ -506,7 +506,7 @@ enum {
};
#endif
typedef struct CPUXtensaState {
struct CPUArchState {
const XtensaConfig *config;
uint32_t regs[16];
uint32_t pc;
@ -545,7 +545,7 @@ typedef struct CPUXtensaState {
/* Watchpoints for DBREAK registers */
struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
} CPUXtensaState;
};
/**
* XtensaCPU:
@ -553,7 +553,7 @@ typedef struct CPUXtensaState {
*
* An Xtensa CPU.
*/
struct XtensaCPU {
struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@ -722,9 +722,6 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
#define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
#define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
typedef CPUXtensaState CPUArchState;
typedef XtensaCPU ArchCPU;
#include "exec/cpu-all.h"
static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,

1
tests/unit/ptimer-test-stubs.c
View File

@ -12,7 +12,6 @@
#include "qemu/main-loop.h"
#include "sysemu/replay.h"
#include "migration/vmstate.h"
#include "sysemu/cpu-timers.h"
#include "ptimer-test.h"