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riscv: sifive_test: Add reset functionality

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This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Bin Meng 2019-09-05 08:55:16 -07:00 committed by Palmer Dabbelt
parent df42fdd6cc
commit 9a2551ed6f
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GPG Key ID: EF4CA1502CCBAB41
2 changed files with 6 additions and 1 deletions
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4
hw/riscv/sifive_test.c
View File

@ -22,6 +22,7 @@
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
#include "qemu/module.h" #include "qemu/module.h"
#include "sysemu/runstate.h"
#include "target/riscv/cpu.h" #include "target/riscv/cpu.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/riscv/sifive_test.h" #include "hw/riscv/sifive_test.h"
@ -42,6 +43,9 @@ static void sifive_test_write(void *opaque, hwaddr addr,
exit(code); exit(code);
case FINISHER_PASS: case FINISHER_PASS:
exit(0); exit(0);
case FINISHER_RESET:
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
return;
default: default:
break; break;
} }

3
include/hw/riscv/sifive_test.h
View File

@ -36,7 +36,8 @@ typedef struct SiFiveTestState {
enum { enum {
FINISHER_FAIL = 0x3333, FINISHER_FAIL = 0x3333,
FINISHER_PASS = 0x5555 FINISHER_PASS = 0x5555,
FINISHER_RESET = 0x7777
}; };
DeviceState *sifive_test_create(hwaddr addr); DeviceState *sifive_test_create(hwaddr addr);