hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505
The MPS2 AN505 FPGA image includes a "FPGA control block" which is a small set of registers handling LEDs, buttons and some counters. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-14-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
5edb1b3fa9
commit
9a52d9992f
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@ -102,6 +102,7 @@ CONFIG_STM32F205_SOC=y
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CONFIG_CMSDK_APB_TIMER=y
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CONFIG_CMSDK_APB_UART=y
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CONFIG_MPS2_FPGAIO=y
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CONFIG_MPS2_SCC=y
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CONFIG_VERSATILE_PCI=y
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@ -58,6 +58,7 @@ obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
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obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
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obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
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obj-$(CONFIG_MIPS_ITU) += mips_itu.o
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obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o
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obj-$(CONFIG_MPS2_SCC) += mps2-scc.o
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obj-$(CONFIG_PVPANIC) += pvpanic.o
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@ -0,0 +1,176 @@
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/*
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* ARM MPS2 AN505 FPGAIO emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/* This is a model of the "FPGA system control and I/O" block found
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* in the AN505 FPGA image for the MPS2 devboard.
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* It is documented in AN505:
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* http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "hw/sysbus.h"
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#include "hw/registerfields.h"
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#include "hw/misc/mps2-fpgaio.h"
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REG32(LED0, 0)
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REG32(BUTTON, 8)
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REG32(CLK1HZ, 0x10)
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REG32(CLK100HZ, 0x14)
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REG32(COUNTER, 0x18)
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REG32(PRESCALE, 0x1c)
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REG32(PSCNTR, 0x20)
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REG32(MISC, 0x4c)
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static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size)
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{
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MPS2FPGAIO *s = MPS2_FPGAIO(opaque);
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uint64_t r;
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switch (offset) {
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case A_LED0:
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r = s->led0;
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break;
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case A_BUTTON:
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/* User-pressable board buttons. We don't model that, so just return
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* zeroes.
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*/
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r = 0;
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break;
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case A_PRESCALE:
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r = s->prescale;
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break;
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case A_MISC:
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r = s->misc;
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break;
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case A_CLK1HZ:
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case A_CLK100HZ:
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case A_COUNTER:
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case A_PSCNTR:
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/* These are all upcounters of various frequencies. */
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qemu_log_mask(LOG_UNIMP, "MPS2 FPGAIO: counters unimplemented\n");
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r = 0;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"MPS2 FPGAIO read: bad offset %x\n", (int) offset);
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r = 0;
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break;
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}
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trace_mps2_fpgaio_read(offset, r, size);
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return r;
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}
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static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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MPS2FPGAIO *s = MPS2_FPGAIO(opaque);
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trace_mps2_fpgaio_write(offset, value, size);
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switch (offset) {
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case A_LED0:
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/* LED bits [1:0] control board LEDs. We don't currently have
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* a mechanism for displaying this graphically, so use a trace event.
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*/
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trace_mps2_fpgaio_leds(value & 0x02 ? '*' : '.',
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value & 0x01 ? '*' : '.');
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s->led0 = value & 0x3;
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break;
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case A_PRESCALE:
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s->prescale = value;
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break;
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case A_MISC:
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/* These are control bits for some of the other devices on the
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* board (SPI, CLCD, etc). We don't implement that yet, so just
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* make the bits read as written.
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*/
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qemu_log_mask(LOG_UNIMP,
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"MPS2 FPGAIO: MISC control bits unimplemented\n");
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s->misc = value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"MPS2 FPGAIO write: bad offset 0x%x\n", (int) offset);
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break;
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}
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}
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static const MemoryRegionOps mps2_fpgaio_ops = {
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.read = mps2_fpgaio_read,
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.write = mps2_fpgaio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void mps2_fpgaio_reset(DeviceState *dev)
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{
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MPS2FPGAIO *s = MPS2_FPGAIO(dev);
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trace_mps2_fpgaio_reset();
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s->led0 = 0;
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s->prescale = 0;
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s->misc = 0;
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}
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static void mps2_fpgaio_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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MPS2FPGAIO *s = MPS2_FPGAIO(obj);
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memory_region_init_io(&s->iomem, obj, &mps2_fpgaio_ops, s,
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"mps2-fpgaio", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription mps2_fpgaio_vmstate = {
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.name = "mps2-fpgaio",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(led0, MPS2FPGAIO),
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VMSTATE_UINT32(prescale, MPS2FPGAIO),
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VMSTATE_UINT32(misc, MPS2FPGAIO),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property mps2_fpgaio_properties[] = {
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/* Frequency of the prescale counter */
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DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mps2_fpgaio_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &mps2_fpgaio_vmstate;
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dc->reset = mps2_fpgaio_reset;
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dc->props = mps2_fpgaio_properties;
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}
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static const TypeInfo mps2_fpgaio_info = {
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.name = TYPE_MPS2_FPGAIO,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MPS2FPGAIO),
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.instance_init = mps2_fpgaio_init,
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.class_init = mps2_fpgaio_class_init,
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};
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static void mps2_fpgaio_register_types(void)
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{
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type_register_static(&mps2_fpgaio_info);
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}
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type_init(mps2_fpgaio_register_types);
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@ -62,6 +62,12 @@ mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2,
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mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config write: function %d device %d data 0x%" PRIx32
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mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC config read: function %d device %d data 0x%" PRIx32
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# hw/misc/mps2_fpgaio.c
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mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
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mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
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mps2_fpgaio_reset(void) "MPS2 FPGAIO: reset"
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mps2_fpgaio_leds(char led1, char led0) "MPS2 FPGAIO LEDs: %c%c"
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# hw/misc/msf2-sysreg.c
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msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32
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msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32
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@ -0,0 +1,43 @@
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/*
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* ARM MPS2 FPGAIO emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/* This is a model of the FPGAIO register block in the AN505
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* FPGA image for the MPS2 dev board; it is documented in the
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* application note:
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* http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
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*
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* QEMU interface:
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* + sysbus MMIO region 0: the register bank
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*/
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#ifndef MPS2_FPGAIO_H
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#define MPS2_FPGAIO_H
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#include "hw/sysbus.h"
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#define TYPE_MPS2_FPGAIO "mps2-fpgaio"
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#define MPS2_FPGAIO(obj) OBJECT_CHECK(MPS2FPGAIO, (obj), TYPE_MPS2_FPGAIO)
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typedef struct {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t led0;
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uint32_t prescale;
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uint32_t misc;
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uint32_t prescale_clk;
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} MPS2FPGAIO;
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#endif
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