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hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models 

Add an orgate and 'or' the interrupts from the BBRAM and RTC models.

Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20220121161141.14389-3-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Francisco Iglesias 2022-01-21 16:11:33 +00:00 committed by Peter Maydell
parent 8c1c0a1b72
commit 9a6d491831
3 changed files with 30 additions and 5 deletions
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2
hw/arm/xlnx-versal-virt.c
View File

@ -365,7 +365,7 @@ static void fdt_add_bbram_node(VersalVirt *s)
qemu_fdt_add_subnode(s->fdt, name);
qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
GIC_FDT_IRQ_TYPE_SPI, VERSAL_BBRAM_APB_IRQ_0,
GIC_FDT_IRQ_TYPE_SPI, VERSAL_PMC_APB_IRQ,
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
qemu_fdt_setprop(s->fdt, name, "interrupt-names",
interrupt_names, sizeof(interrupt_names));

28
hw/arm/xlnx-versal.c
View File

@ -25,6 +25,8 @@
#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
#define GEM_REVISION 0x40070106
#define VERSAL_NUM_PMC_APB_IRQS 2
static void versal_create_apu_cpus(Versal *s)
{
int i;
@ -260,6 +262,25 @@ static void versal_create_sds(Versal *s, qemu_irq *pic)
}
}
static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic)
{
DeviceState *orgate;
/*
* The VERSAL_PMC_APB_IRQ is an 'or' of the interrupts from the following
* models:
* - RTC
* - BBRAM
*/
object_initialize_child(OBJECT(s), "pmc-apb-irq-orgate",
&s->pmc.apb_irq_orgate, TYPE_OR_IRQ);
orgate = DEVICE(&s->pmc.apb_irq_orgate);
object_property_set_int(OBJECT(orgate),
"num-lines", VERSAL_NUM_PMC_APB_IRQS, &error_fatal);
qdev_realize(orgate, NULL, &error_fatal);
qdev_connect_gpio_out(orgate, 0, pic[VERSAL_PMC_APB_IRQ]);
}
static void versal_create_rtc(Versal *s, qemu_irq *pic)
{
SysBusDevice *sbd;
@ -277,7 +298,8 @@ static void versal_create_rtc(Versal *s, qemu_irq *pic)
* TODO: Connect the ALARM and SECONDS interrupts once our RTC model
* supports them.
*/
sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]);
sysbus_connect_irq(sbd, 1,
qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 0));
}
static void versal_create_xrams(Versal *s, qemu_irq *pic)
@ -328,7 +350,8 @@ static void versal_create_bbram(Versal *s, qemu_irq *pic)
sysbus_realize(sbd, &error_fatal);
memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL,
sysbus_mmio_get_region(sbd, 0));
sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]);
sysbus_connect_irq(sbd, 0,
qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 1));
}
static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base)
@ -455,6 +478,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
versal_create_gems(s, pic);
versal_create_admas(s, pic);
versal_create_sds(s, pic);
versal_create_pmc_apb_irq_orgate(s, pic);
versal_create_rtc(s, pic);
versal_create_xrams(s, pic);
versal_create_bbram(s, pic);

5
include/hw/arm/xlnx-versal.h
View File

@ -85,6 +85,8 @@ struct Versal {
XlnxEFuse efuse;
XlnxVersalEFuseCtrl efuse_ctrl;
XlnxVersalEFuseCache efuse_cache;
qemu_or_irq apb_irq_orgate;
} pmc;
struct {
@ -111,8 +113,7 @@ struct Versal {
#define VERSAL_GEM1_WAKE_IRQ_0 59
#define VERSAL_ADMA_IRQ_0 60
#define VERSAL_XRAM_IRQ_0 79
#define VERSAL_BBRAM_APB_IRQ_0 121
#define VERSAL_RTC_APB_ERR_IRQ 121
#define VERSAL_PMC_APB_IRQ 121
#define VERSAL_SD0_IRQ_0 126
#define VERSAL_EFUSE_IRQ 139
#define VERSAL_RTC_ALARM_IRQ 142