OpenE2K/qemu-e2k
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Name the magic constants, fix a hex number without 0x

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3677 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2007-11-17 21:01:04 +00:00
parent e1dad5a615
commit 9a87ce9b95
1 changed files with 16 additions and 10 deletions
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26
hw/slavio_intctl.c
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@ -68,6 +68,12 @@ typedef struct SLAVIO_INTCTLState {
#define INTCTLM_MAXADDR 0x13 #define INTCTLM_MAXADDR 0x13
#define INTCTLM_SIZE (INTCTLM_MAXADDR + 1) #define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
#define INTCTLM_MASK 0x1f #define INTCTLM_MASK 0x1f
#define MASTER_IRQ_MASK ~0x4fb2007f
#define MASTER_DISABLE 0x80000000
#define CPU_IRQ_MASK 0xfffe0000
#define CPU_IRQ_INT15_IN 0x0004000
#define CPU_IRQ_INT15_MASK 0x80000000
static void slavio_check_interrupts(void *opaque); static void slavio_check_interrupts(void *opaque);
// per-cpu interrupt controller // per-cpu interrupt controller
@ -103,15 +109,15 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint
DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val); DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
switch (saddr) { switch (saddr) {
case 1: // clear pending softints case 1: // clear pending softints
if (val & 0x4000) if (val & CPU_IRQ_INT15_IN)
val |= 80000000; val |= CPU_IRQ_INT15_MASK;
val &= 0xfffe0000; val &= CPU_IRQ_MASK;
s->intreg_pending[cpu] &= ~val; s->intreg_pending[cpu] &= ~val;
slavio_check_interrupts(s); slavio_check_interrupts(s);
DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
break; break;
case 2: // set softint case 2: // set softint
val &= 0xfffe0000; val &= CPU_IRQ_MASK;
s->intreg_pending[cpu] |= val; s->intreg_pending[cpu] |= val;
slavio_check_interrupts(s); slavio_check_interrupts(s);
DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]); DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
@ -142,7 +148,7 @@ static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
saddr = (addr & INTCTLM_MAXADDR) >> 2; saddr = (addr & INTCTLM_MAXADDR) >> 2;
switch (saddr) { switch (saddr) {
case 0: case 0:
ret = s->intregm_pending & 0x7fffffff; ret = s->intregm_pending & ~MASTER_DISABLE;
break; break;
case 1: case 1:
ret = s->intregm_disabled; ret = s->intregm_disabled;
@ -169,14 +175,14 @@ static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uin
switch (saddr) { switch (saddr) {
case 2: // clear (enable) case 2: // clear (enable)
// Force clear unused bits // Force clear unused bits
val &= ~0x4fb2007f; val &= MASTER_IRQ_MASK;
s->intregm_disabled &= ~val; s->intregm_disabled &= ~val;
DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled); DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
slavio_check_interrupts(s); slavio_check_interrupts(s);
break; break;
case 3: // set (disable, clear pending) case 3: // set (disable, clear pending)
// Force clear unused bits // Force clear unused bits
val &= ~0x4fb2007f; val &= MASTER_IRQ_MASK;
s->intregm_disabled |= val; s->intregm_disabled |= val;
s->intregm_pending &= ~val; s->intregm_pending &= ~val;
slavio_check_interrupts(s); slavio_check_interrupts(s);
@ -244,14 +250,14 @@ static void slavio_check_interrupts(void *opaque)
DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled); DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
for (i = 0; i < MAX_CPUS; i++) { for (i = 0; i < MAX_CPUS; i++) {
pil_pending = 0; pil_pending = 0;
if (pending && !(s->intregm_disabled & 0x80000000) && if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
(i == s->target_cpu)) { (i == s->target_cpu)) {
for (j = 0; j < 32; j++) { for (j = 0; j < 32; j++) {
if (pending & (1 << j)) if (pending & (1 << j))
pil_pending |= 1 << s->intbit_to_level[j]; pil_pending |= 1 << s->intbit_to_level[j];
} }
} }
pil_pending |= (s->intreg_pending[i] >> 16) & 0xfffe; pil_pending |= (s->intreg_pending[i] & CPU_IRQ_MASK) >> 16;
for (j = 0; j < MAX_PILS; j++) { for (j = 0; j < MAX_PILS; j++) {
if (pil_pending & (1 << j)) { if (pil_pending & (1 << j)) {
@ -346,7 +352,7 @@ static void slavio_intctl_reset(void *opaque)
for (i = 0; i < MAX_CPUS; i++) { for (i = 0; i < MAX_CPUS; i++) {
s->intreg_pending[i] = 0; s->intreg_pending[i] = 0;
} }
s->intregm_disabled = ~0xffb2007f; s->intregm_disabled = ~MASTER_IRQ_MASK;
s->intregm_pending = 0; s->intregm_pending = 0;
s->target_cpu = 0; s->target_cpu = 0;
slavio_check_interrupts(s); slavio_check_interrupts(s);