OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target-arm queue: 

* Remove can't-happen if() from handle_vec_simd_shli()
  * hw/arm/exynos4210: Zero memory allocated for Exynos4210State
  * Set S and PTW in 64-bit PAR format
  * Fix ATS1Hx instructions
  * milkymist: Check for failure trying to load BIOS image
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABCAAGBQJb4Xz6AAoJEDwlJe0UNgzecj4P/ApIjAZbPAYLPjhMoA9SZmY1
 O2tlcPieYZQZu+GM28TW8URMEK3ter/6rBMuwDsX6qsvyaGE65MV2UDCTjDq2yIt
 dE29xOYn8wrSz/xiuMnDU/V26kjyZYtteYo6lS/TWmFeftuhdSXyFX3Lq7KyQ7fE
 dOkb9eI6/XNiRajw9kC3OubUIgMpkGz641i9wMa1RY2lq4TtJH1qR6WWl3hHR9o2
 riY3BupD7COcFW8ZUjGC+0dl1AqlokVuLojjDGYmzCY6sBnAYyTnxheZmtgcK0RC
 Bju5Gnrhw7N9YEiIdThni4hp9s45+u2VifxOXp8Bpa6bkriomkArJYBn+GqNvuox
 WDp9ijWlesl3N3B3BlSN3cq2l8I+HRtX/yzWvSgjtEjjQ5IkOHgoPPYCL0N38jlI
 2/nLKkTB1ltoGLkj15Vco3bmDhx1fonlr9PdtHoEoJWQZVzNk8JU72wQiKlqIzMt
 GbiabB66IaWNgcoXIwu/6NiG7QSZ4zbo4HYqwY9lXS9pCLCAZQF23nfOJmNmqm6E
 lrZOjnkO+Q8u6J6Km+zpd6V3Ml2aPJGuRoMsx5qLhSm3poyYgW29jojYNzSAGdDs
 k4jhfT1ZfHyjK/hRJGIVr5fEbNpJMHAXdlVxveU04QysL/NPtGfCAtmqia/R7tye
 gjcQ4+TzPQY0Ad03/GdW
 =7I2F
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181106' into staging

target-arm queue:
 * Remove can't-happen if() from handle_vec_simd_shli()
 * hw/arm/exynos4210: Zero memory allocated for Exynos4210State
 * Set S and PTW in 64-bit PAR format
 * Fix ATS1Hx instructions
 * milkymist: Check for failure trying to load BIOS image

# gpg: Signature made Tue 06 Nov 2018 11:37:30 GMT
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20181106:
  target/arm: Fix ATS1Hx instructions
  target/arm: Set S and PTW in 64-bit PAR format
  hw/arm/exynos4210: Zero memory allocated for Exynos4210State
  milkymist: Check for failure trying to load BIOS image
  target/arm: Remove can't-happen if() from handle_vec_simd_shli()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2018-11-06 12:39:36 +00:00
parent b66db50f67 23463e0e4a
commit 9aca866699
4 changed files with 16 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/arm/exynos4210.c
View File

@ -162,7 +162,7 @@ static uint64_t exynos4210_calc_affinity(int cpu)
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
{
Exynos4210State *s = g_new(Exynos4210State, 1);
Exynos4210State *s = g_new0(Exynos4210State, 1);
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
SysBusDevice *busdev;
DeviceState *dev;

5
hw/lm32/milkymist.c
View File

@ -138,7 +138,10 @@ milkymist_init(MachineState *machine)
bios_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (bios_filename) {
load_image_targphys(bios_filename, BIOS_OFFSET, BIOS_SIZE);
if (load_image_targphys(bios_filename, BIOS_OFFSET, BIOS_SIZE) < 0) {
error_report("could not load bios '%s'", bios_filename);
exit(1);
}
}
reset_info->bootstrap_pc = BIOS_OFFSET;

14
target/arm/helper.c
View File

@ -2319,7 +2319,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
*
* (Note that HCR.DC makes HCR.VM behave as if it is 1.)
*
* ATS1Hx always uses the 64bit format (not supported yet).
* ATS1Hx always uses the 64bit format.
*/
format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
@ -2347,10 +2347,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
par64 |= 1; /* F */
par64 |= (fsr & 0x3f) << 1; /* FS */
/* Note that S2WLK and FSTAGE are always zero, because we don't
* implement virtualization and therefore there can't be a stage 2
* fault.
*/
if (fi.stage2) {
par64 |= (1 << 9); /* S */
}
if (fi.s1ptw) {
par64 |= (1 << 8); /* PTW */
}
}
} else {
/* fsr is a DFSR/IFSR value for the short descriptor
@ -2442,7 +2444,7 @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
uint64_t par64;
par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S1E2);
A32_BANKED_CURRENT_REG_SET(env, par, par64);
}

8
target/arm/translate-a64.c
View File

@ -9483,12 +9483,10 @@ static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
int immhb = immh << 3 | immb;
int shift = immhb - (8 << size);
if (extract32(immh, 3, 1) && !is_q) {
unallocated_encoding(s);
return;
}
/* Range of size is limited by decode: immh is a non-zero 4 bit field */
assert(size >= 0 && size <= 3);
if (size > 3 && !is_q) {
if (extract32(immh, 3, 1) && !is_q) {
unallocated_encoding(s);
return;
}