Seventh RISC-V PR for QEMU 7.1

This is a second PR to go in for RC1. It fixes a bug we have had
 for awhile, but it's a simple fix so let's pull it in for RC1.
 
 * linux-user/riscv: Align signal frame to 16 bytes
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Merge tag 'pull-riscv-to-apply-20220802' of github.com:alistair23/qemu into staging

Seventh RISC-V PR for QEMU 7.1

This is a second PR to go in for RC1. It fixes a bug we have had
for awhile, but it's a simple fix so let's pull it in for RC1.

* linux-user/riscv: Align signal frame to 16 bytes

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# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
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* tag 'pull-riscv-to-apply-20220802' of github.com:alistair23/qemu:
  linux-user/riscv: Align signal frame to 16 bytes

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-08-01 19:05:10 -07:00
commit 9b00d27901
1 changed files with 1 additions and 3 deletions

View File

@ -64,9 +64,7 @@ static abi_ulong get_sigframe(struct target_sigaction *ka,
/* This is the X/Open sanctioned signal stack switching. */
sp = target_sigsp(sp, ka) - framesize;
/* XXX: kernel aligns with 0xf ? */
sp &= ~3UL; /* align sp on 4-byte boundary */
sp &= ~0xf;
return sp;
}