apb: rename apb.c to sabre.c
This is the final stage in correcting the naming convention with respect to sabre, APB and PBM. It is effectively a file rename from apb.c to sabre.c along with touching up a few constants to remove the remaining references to APB. Note that as part of the rename process the configuration variable CONFIG_PCI_APB is changed to CONFIG_PCI_SABRE. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
This commit is contained in:
Mark Cave-Ayland
parent
5795162a9f
commit
9b30179460
@ -11,7 +11,7 @@ CONFIG_PCKBD=y
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CONFIG_FDC=y
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CONFIG_IDE_ISA=y
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CONFIG_IDE_CMD646=y
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CONFIG_PCI_APB=y
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CONFIG_PCI_SABRE=y
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CONFIG_SIMBA=y
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CONFIG_SUNHME=y
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CONFIG_MC146818RTC=y
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@ -11,7 +11,7 @@ common-obj-$(CONFIG_PPCE500_PCI) += ppce500.o
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# ARM devices
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common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o
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common-obj-$(CONFIG_PCI_APB) += apb.o
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common-obj-$(CONFIG_PCI_SABRE) += sabre.o
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common-obj-$(CONFIG_FULONG) += bonito.o
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common-obj-$(CONFIG_PCI_PIIX) += piix.o
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common-obj-$(CONFIG_PCI_Q35) += q35.o
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@ -1,8 +1,9 @@
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/*
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* QEMU Ultrasparc APB PCI host
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* QEMU Ultrasparc Sabre PCI host (PBM)
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2012,2013 Artyom Tarasenko
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* Copyright (c) 2018 Mark Cave-Ayland
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -23,10 +24,6 @@
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* THE SOFTWARE.
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*/
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/* XXX This file and most of its contents are somewhat misnamed. The
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Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
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the secondary PCI bridge. */
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/pci/pci.h"
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@ -34,20 +31,20 @@
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci-bridge/simba.h"
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#include "hw/pci-host/apb.h"
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#include "hw/pci-host/sabre.h"
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#include "sysemu/sysemu.h"
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#include "exec/address-spaces.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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/* debug APB */
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//#define DEBUG_APB
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/* debug sabre */
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//#define DEBUG_SABRE
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#ifdef DEBUG_APB
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#define APB_DPRINTF(fmt, ...) \
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do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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#ifdef DEBUG_SABRE
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#define SABRE_DPRINTF(fmt, ...) \
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do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define APB_DPRINTF(fmt, ...)
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#define SABRE_DPRINTF(fmt, ...)
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#endif
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/*
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@ -72,7 +69,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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static inline void sabre_set_request(SabreState *s, unsigned int irq_num)
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{
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APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
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SABRE_DPRINTF("%s: request irq %d\n", __func__, irq_num);
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s->irq_request = irq_num;
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qemu_set_irq(s->ivec_irqs[irq_num], 1);
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@ -111,7 +108,7 @@ static inline void sabre_check_irqs(SabreState *s)
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static inline void sabre_clear_request(SabreState *s, unsigned int irq_num)
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{
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APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
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SABRE_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
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qemu_set_irq(s->ivec_irqs[irq_num], 0);
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s->irq_request = NO_IRQ_REQUEST;
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}
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@ -128,7 +125,8 @@ static void sabre_config_write(void *opaque, hwaddr addr,
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{
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SabreState *s = opaque;
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APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
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SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,
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addr, val);
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switch (addr & 0xffff) {
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case 0x30 ... 0x4f: /* DMA error registers */
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@ -252,7 +250,7 @@ static uint64_t sabre_config_read(void *opaque,
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val = 0;
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break;
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}
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APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
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SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
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return val;
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}
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@ -269,7 +267,8 @@ static void sabre_pci_config_write(void *opaque, hwaddr addr,
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SabreState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
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SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,
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addr, val);
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pci_data_write(phb->bus, addr, val, size);
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}
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@ -281,7 +280,7 @@ static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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ret = pci_data_read(phb->bus, addr, size);
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APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
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SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
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return ret;
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}
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@ -319,7 +318,7 @@ static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
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{
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SabreState *s = opaque;
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APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
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SABRE_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
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/* PCI IRQ map onto the first 32 INO. */
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if (irq_num < 32) {
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if (level) {
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@ -333,7 +332,8 @@ static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
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} else {
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/* OBIO IRQ map onto the next 32 INO. */
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if (level) {
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APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
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SABRE_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num,
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level);
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s->pci_irq_in |= 1ULL << irq_num;
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if ((s->irq_request == NO_IRQ_REQUEST)
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&& (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
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@ -390,7 +390,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
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SysBusDevice *sbd = SYS_BUS_DEVICE(s);
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PCIDevice *pci_dev;
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/* apb_config */
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/* sabre_config */
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sysbus_mmio_map(sbd, 0, s->special_base);
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/* PCI configuration space */
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sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL);
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@ -410,7 +410,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
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pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
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/* IOMMU */
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memory_region_add_subregion_overlap(&s->apb_config, 0x200,
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memory_region_add_subregion_overlap(&s->sabre_config, 0x200,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1);
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pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu);
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@ -454,19 +454,20 @@ static void sabre_init(Object *obj)
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qdev_prop_allow_set_link_before_realize,
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0, NULL);
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/* apb_config */
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memory_region_init_io(&s->apb_config, OBJECT(s), &sabre_config_ops, s,
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"apb-config", 0x10000);
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/* sabre_config */
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memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s,
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"sabre-config", 0x10000);
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/* at region 0 */
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sysbus_init_mmio(sbd, &s->apb_config);
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sysbus_init_mmio(sbd, &s->sabre_config);
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memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s,
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"apb-pci-config", 0x1000000);
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"sabre-pci-config", 0x1000000);
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/* at region 1 */
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sysbus_init_mmio(sbd, &s->pci_config);
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/* pci_ioport */
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memory_region_init(&s->pci_ioport, OBJECT(s), "apb-pci-ioport", 0x1000000);
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memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport",
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0x1000000);
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/* at region 2 */
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sysbus_init_mmio(sbd, &s->pci_ioport);
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@ -30,7 +30,7 @@
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_host.h"
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#include "hw/pci-host/apb.h"
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#include "hw/pci-host/sabre.h"
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#include "hw/i386/pc.h"
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#include "hw/char/serial.h"
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#include "hw/timer/m48t59.h"
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@ -27,7 +27,7 @@ typedef struct SabreState {
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hwaddr special_base;
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hwaddr mem_base;
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MemoryRegion apb_config;
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MemoryRegion sabre_config;
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MemoryRegion pci_config;
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MemoryRegion pci_mmio;
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MemoryRegion pci_ioport;
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