hw/other: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
6eedbb5b0c
commit
9b4b4e510b
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@ -312,7 +312,7 @@ build_prepend_package_length(GArray *package, unsigned length, bool incl_self)
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/*
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* PkgLength is the length of the inclusive length of the data
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* and PkgLength's length itself when used for terms with
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* explitit length.
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* explicit length.
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*/
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length += length_bytes;
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}
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@ -680,7 +680,7 @@ Aml *aml_store(Aml *val, Aml *target)
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* "Op Operand Operand Target"
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* pattern.
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*
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* Returns: The newly allocated and composed according to patter Aml object.
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* Returns: The newly allocated and composed according to pattern Aml object.
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*/
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static Aml *
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build_opcode_2arg_dst(uint8_t op, Aml *arg1, Aml *arg2, Aml *dst)
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@ -2159,7 +2159,7 @@ void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f,
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/* FADT Minor Version */
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build_append_int_noprefix(tbl, f->minor_ver, 1);
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} else {
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build_append_int_noprefix(tbl, 0, 3); /* Reserved upto ACPI 5.0 */
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build_append_int_noprefix(tbl, 0, 3); /* Reserved up to ACPI 5.0 */
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}
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build_append_int_noprefix(tbl, 0, 8); /* X_FIRMWARE_CTRL */
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@ -82,7 +82,7 @@ static void build_hmat_lb(GArray *table_data, HMAT_LB_Info *hmat_lb,
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uint32_t base;
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/* Length in bytes for entire structure */
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uint32_t lb_length
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= 32 /* Table length upto and including Entry Base Unit */
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= 32 /* Table length up to and including Entry Base Unit */
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+ 4 * num_initiator /* Initiator Proximity Domain List */
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+ 4 * num_target /* Target Proximity Domain List */
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+ 2 * num_initiator * num_target; /* Latency or Bandwidth Entries */
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@ -1102,7 +1102,7 @@ static void nvdimm_build_common_dsm(Aml *dev,
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* be treated as an integer. Moreover, the integer size depends on
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* DSDT tables revision number. If revision number is < 2, integer
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* size is 32 bits, otherwise it is 64 bits.
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* Because of this CreateField() canot be used if RLEN < Integer Size.
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* Because of this CreateField() cannot be used if RLEN < Integer Size.
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*
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* Also please note that APCI ASL operator SizeOf() doesn't support
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* Integer and there isn't any other way to figure out the Integer
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@ -50,7 +50,7 @@ struct partition {
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uint32_t nr_sects; /* nr of sectors in partition */
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} QEMU_PACKED;
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/* try to guess the disk logical geometry from the MSDOS partition table.
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/* try to guess the disk logical geometry from the MS-DOS partition table.
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Return 0 if OK, -1 if could not guess */
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static int guess_disk_lchs(BlockBackend *blk,
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int *pcylinders, int *pheads, int *psectors)
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@ -66,7 +66,7 @@ static int guess_disk_lchs(BlockBackend *blk,
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if (blk_pread(blk, 0, BDRV_SECTOR_SIZE, buf, 0) < 0) {
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return -1;
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}
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/* test msdos magic */
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/* test MS-DOS magic */
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if (buf[510] != 0x55 || buf[511] != 0xaa) {
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return -1;
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}
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@ -891,7 +891,7 @@ static Property pflash_cfi01_properties[] = {
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/* num-blocks is the number of blocks actually visible to the guest,
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* ie the total size of the device divided by the sector length.
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* If we're emulating flash devices wired in parallel the actual
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* number of blocks per indvidual device will differ.
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* number of blocks per individual device will differ.
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*/
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DEFINE_PROP_UINT32("num-blocks", PFlashCFI01, nb_blocs, 0),
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DEFINE_PROP_UINT64("sector-length", PFlashCFI01, sector_len, 0),
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@ -575,7 +575,7 @@ static int cadence_uart_pre_load(void *opaque)
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{
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CadenceUARTState *s = opaque;
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/* the frequency will be overriden if the refclk field is present */
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/* the frequency will be overridden if the refclk field is present */
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clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK);
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return 0;
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}
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@ -112,7 +112,7 @@ static void imx_serial_reset_at_boot(DeviceState *dev)
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imx_serial_reset(s);
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/*
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* enable the uart on boot, so messages from the linux decompresser
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* enable the uart on boot, so messages from the linux decompressor
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* are visible. On real hardware this is done by the boot rom
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* before anything else is loaded.
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*/
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@ -54,7 +54,7 @@
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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#define UART_IIR_CTI 0x0C /* Character Timeout Indication */
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#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
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#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functioning */
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#define UART_IIR_FE 0xC0 /* Fifo enabled */
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/*
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@ -24,7 +24,7 @@
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* callback that does the memory operations.
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* This device allows the user to monkey patch memory. To be able to do
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* this it needs a backend to manage the datas, the same as other
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* this it needs a backend to manage the data, the same as other
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* memory-related devices. In this case as the backend is so trivial we
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* have merged it with the frontend instead of creating and maintaining a
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* separate backend.
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@ -166,7 +166,7 @@ static void generic_loader_realize(DeviceState *dev, Error **errp)
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}
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}
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/* Convert the data endiannes */
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/* Convert the data endianness */
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if (s->data_be) {
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s->data = cpu_to_be64(s->data);
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} else {
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@ -1426,7 +1426,7 @@ void machine_run_board_init(MachineState *machine, const char *mem_path, Error *
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for (i = 0; machine_class->valid_cpu_types[i]; i++) {
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if (object_class_dynamic_cast(oc,
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machine_class->valid_cpu_types[i])) {
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/* The user specificed CPU is in the valid field, we are
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/* The user specified CPU is in the valid field, we are
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* good to go.
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*/
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break;
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@ -107,7 +107,7 @@ static void set_drive_helper(Object *obj, Visitor *v, const char *name,
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}
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if (*ptr) {
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/* BlockBackend alread exists. So, we want to change attached node */
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/* BlockBackend already exists. So, we want to change attached node */
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blk = *ptr;
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ctx = blk_get_aio_context(blk);
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bs = bdrv_lookup_bs(NULL, str, errp);
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@ -161,7 +161,7 @@ static void a15mp_priv_class_init(ObjectClass *klass, void *data)
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dc->realize = a15mp_priv_realize;
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device_class_set_props(dc, a15mp_priv_properties);
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/* We currently have no savable state */
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/* We currently have no saveable state */
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}
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static const TypeInfo a15mp_priv_info = {
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@ -197,7 +197,7 @@ CXLRetCode cxl_event_clear_records(CXLDeviceState *cxlds, CXLClearEventPayload *
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QEMU_LOCK_GUARD(&log->lock);
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/*
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* Must itterate the queue twice.
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* Must iterate the queue twice.
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* "The device shall verify the event record handles specified in the input
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* payload are in temporal order. If the device detects an older event
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* record that will not be cleared when Clear Event Records is executed,
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@ -39,7 +39,7 @@
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* fill the output data into cmd->payload (overwriting what was there),
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* setting the length, and returning a valid return code.
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*
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* XXX: The handler need not worry about endianess. The payload is read out of
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* XXX: The handler need not worry about endianness. The payload is read out of
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* a register interface that already deals with it.
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*/
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@ -501,7 +501,7 @@ static CXLRetCode cmd_media_get_poison_list(struct cxl_cmd *cmd,
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uint16_t out_pl_len;
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query_start = ldq_le_p(&in->pa);
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/* 64 byte alignemnt required */
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/* 64 byte alignment required */
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if (query_start & 0x3f) {
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return CXL_MBOX_INVALID_INPUT;
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}
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@ -247,7 +247,7 @@ static void omap_dma_deactivate_channel(struct omap_dma_s *s,
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return;
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}
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/* Don't deactive the channel if it is synchronized and the DMA request is
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/* Don't deactivate the channel if it is synchronized and the DMA request is
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active */
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if (ch->sync && ch->enable && (s->dma->drqbmp & (1ULL << ch->sync)))
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return;
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@ -422,7 +422,7 @@ static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma)
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if (ch->fs && ch->bs) {
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a->pck_element ++;
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/* Check if a full packet has beed transferred. */
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/* Check if a full packet has been transferred. */
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if (a->pck_element == a->pck_elements) {
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a->pck_element = 0;
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@ -209,7 +209,7 @@ static void hid_pointer_sync(DeviceState *dev)
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prev->dz += curr->dz;
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curr->dz = 0;
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} else {
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/* prepate next (clear rel, copy abs + btns) */
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/* prepare next (clear rel, copy abs + btns) */
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if (hs->kind == HID_MOUSE) {
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next->xdx = 0;
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next->ydy = 0;
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@ -157,14 +157,14 @@ static uint16_t tsc2005_read(TSC2005State *s, int reg)
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s->reset = true;
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return ret;
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case 0x8: /* AUX high treshold */
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case 0x8: /* AUX high threshold */
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return s->aux_thr[1];
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case 0x9: /* AUX low treshold */
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case 0x9: /* AUX low threshold */
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return s->aux_thr[0];
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case 0xa: /* TEMP high treshold */
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case 0xa: /* TEMP high threshold */
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return s->temp_thr[1];
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case 0xb: /* TEMP low treshold */
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case 0xb: /* TEMP low threshold */
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return s->temp_thr[0];
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case 0xc: /* CFR0 */
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@ -186,17 +186,17 @@ static uint16_t tsc2005_read(TSC2005State *s, int reg)
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static void tsc2005_write(TSC2005State *s, int reg, uint16_t data)
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{
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switch (reg) {
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case 0x8: /* AUX high treshold */
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case 0x8: /* AUX high threshold */
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s->aux_thr[1] = data;
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break;
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case 0x9: /* AUX low treshold */
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case 0x9: /* AUX low threshold */
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s->aux_thr[0] = data;
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break;
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case 0xa: /* TEMP high treshold */
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case 0xa: /* TEMP high threshold */
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s->temp_thr[1] = data;
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break;
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case 0xb: /* TEMP low treshold */
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case 0xb: /* TEMP low threshold */
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s->temp_thr[0] = data;
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break;
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@ -191,7 +191,7 @@ static MemTxResult extioi_writew(void *opaque, hwaddr addr,
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cpu = attrs.requester_id;
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old_data = s->coreisr[cpu][index];
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s->coreisr[cpu][index] = old_data & ~val;
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/* write 1 to clear interrrupt */
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/* write 1 to clear interrupt */
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old_data &= val;
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irq = ctz32(old_data);
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while (irq != 32) {
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@ -1,5 +1,5 @@
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/*
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* QEMU Loongson Local I/O interrupt controler.
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* QEMU Loongson Local I/O interrupt controller.
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*
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* Copyright (c) 2020 Huacai Chen <chenhc@lemote.com>
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* Copyright (c) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
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@ -68,7 +68,7 @@ static void omap_inth_sir_update(OMAPIntcState *s, int is_fiq)
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p_intr = 255;
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/* Find the interrupt line with the highest dynamic priority.
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* Note: 0 denotes the hightest priority.
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* Note: 0 denotes the highest priority.
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* If all interrupts have the same priority, the default order is IRQ_N,
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* IRQ_N-1,...,IRQ_0. */
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for (j = 0; j < s->nbanks; ++j) {
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@ -988,7 +988,7 @@ static void pnv_xive_ic_reg_write(void *opaque, hwaddr offset,
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*/
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case VC_SBC_CONFIG: /* Store EOI configuration */
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/*
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* Configure store EOI if required by firwmare (skiboot has removed
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* Configure store EOI if required by firmware (skiboot has removed
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* support recently though)
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*/
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if (val & (VC_SBC_CONF_CPLX_CIST | VC_SBC_CONF_CIST_BOTH)) {
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@ -27,7 +27,7 @@
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#include "trace.h"
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/*
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* XIVE Virtualization Controller BAR and Thread Managment BAR that we
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* XIVE Virtualization Controller BAR and Thread Management BAR that we
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* use for the ESB pages and the TIMA pages
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*/
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#define SPAPR_XIVE_VC_BASE 0x0006010000000000ull
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@ -485,7 +485,7 @@ static int kvmppc_xive_get_queues(SpaprXive *xive, Error **errp)
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*
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* Whenever the VM is stopped, the VM change handler sets the source
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* PQs to PENDING to stop the flow of events and to possibly catch a
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* triggered interrupt occuring while the VM is stopped. The previous
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* triggered interrupt occurring while the VM is stopped. The previous
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* state is saved in anticipation of a migration. The XIVE controller
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* is then synced through KVM to flush any in-flight event
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* notification and stabilize the EQs.
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@ -551,7 +551,7 @@ static void kvmppc_xive_change_state_handler(void *opaque, bool running,
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/*
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* PQ is set to PENDING to possibly catch a triggered
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* interrupt occuring while the VM is stopped (hotplug event
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* interrupt occurring while the VM is stopped (hotplug event
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* for instance) .
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*/
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if (pq != XIVE_ESB_OFF) {
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@ -633,7 +633,7 @@ int kvmppc_xive_post_load(SpaprXive *xive, int version_id)
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/* The KVM XIVE device should be in use */
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assert(xive->fd != -1);
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/* Restore the ENDT first. The targetting depends on it. */
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/* Restore the ENDT first. The targeting depends on it. */
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for (i = 0; i < xive->nr_ends; i++) {
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if (!xive_end_is_valid(&xive->endt[i])) {
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continue;
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@ -1608,7 +1608,7 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
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*
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* It receives notification requests sent by the IVRE to find one
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* matching NVT (or more) dispatched on the processor threads. In case
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* of a single NVT notification, the process is abreviated and the
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* of a single NVT notification, the process is abbreviated and the
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* thread is signaled if a match is found. In case of a logical server
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* notification (bits ignored at the end of the NVT identifier), the
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* IVPE and IVRE select a winning thread using different filters. This
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@ -542,7 +542,7 @@ static void xive2_router_realize(DeviceState *dev, Error **errp)
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/*
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* Notification using the END ESe/ESn bit (Event State Buffer for
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* escalation and notification). Profide futher coalescing in the
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* escalation and notification). Profide further coalescing in the
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* Router.
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*/
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static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk,
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@ -621,7 +621,7 @@ static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk,
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/*
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* Check the END ESn (Event State Buffer for notification) for
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* even futher coalescing in the Router
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* even further coalescing in the Router
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*/
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if (!xive2_end_is_notify(&end)) {
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/* ESn[Q]=1 : end of notification */
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@ -702,7 +702,7 @@ do_escalation:
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/*
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* Check the END ESe (Event State Buffer for escalation) for even
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* futher coalescing in the Router
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* further coalescing in the Router
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*/
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if (!xive2_end_is_uncond_escalation(&end)) {
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/* ESe[Q]=1 : end of escalation notification */
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@ -301,7 +301,7 @@ static void handle_msg(IPMIBmcExtern *ibe)
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ipmi_debug("msg checksum failure\n");
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return;
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} else {
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ibe->inpos--; /* Remove checkum */
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ibe->inpos--; /* Remove checksum */
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}
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timer_del(ibe->extern_timer);
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@ -538,7 +538,7 @@ static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value,
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FIRST_ERROR_POINTER, cxl_err->type);
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} else {
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/*
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* If no more errors, then follow recomendation of PCI spec
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* If no more errors, then follow recommendation of PCI spec
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* r6.0 6.2.4.2 to set the first error pointer to a status
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* bit that will never be used.
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*/
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@ -697,7 +697,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
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PCI_BASE_ADDRESS_MEM_TYPE_64,
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&ct3d->cxl_dstate.device_registers);
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/* MSI(-X) Initailization */
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/* MSI(-X) Initialization */
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rc = msix_init_exclusive_bar(pci_dev, msix_num, 4, NULL);
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if (rc) {
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goto err_address_space_free;
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@ -706,7 +706,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
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msix_vector_use(pci_dev, i);
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}
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/* DOE Initailization */
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/* DOE Initialization */
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pcie_doe_init(pci_dev, &ct3d->doe_cdat, 0x190, doe_cdat_prot, true, 0);
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||||
cxl_cstate->cdat.build_cdat_table = ct3_build_cdat_table;
|
||||
|
|
|
@ -227,7 +227,7 @@ static uint32_t imx7_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
|
|||
* have fixed frequencies and we can provide requested frequency
|
||||
* easily. However for CCM provided clocks (like IPG) each GPT
|
||||
* timer can have its own clock root.
|
||||
* This means we need additionnal information when calling this
|
||||
* This means we need additional information when calling this
|
||||
* function to know the requester's identity.
|
||||
*/
|
||||
uint32_t freq = 0;
|
||||
|
|
|
@ -246,7 +246,7 @@
|
|||
#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
|
||||
#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
|
||||
#define vSR 0x1400 /* [VIA only] Shift register. */
|
||||
#define vACR 0x1600 /* [VIA only] Auxilary control register. */
|
||||
#define vACR 0x1600 /* [VIA only] Auxiliary control register. */
|
||||
#define vPCR 0x1800 /* [VIA only] Peripheral control register. */
|
||||
/*
|
||||
* CHRP sez never ever to *write* this.
|
||||
|
|
|
@ -94,12 +94,12 @@ static void stm32f2xx_syscfg_write(void *opaque, hwaddr addr,
|
|||
switch (addr) {
|
||||
case SYSCFG_MEMRMP:
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"%s: Changeing the memory mapping isn't supported " \
|
||||
"%s: Changing the memory mapping isn't supported " \
|
||||
"in QEMU\n", __func__);
|
||||
return;
|
||||
case SYSCFG_PMC:
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"%s: Changeing the memory mapping isn't supported " \
|
||||
"%s: Changing the memory mapping isn't supported " \
|
||||
"in QEMU\n", __func__);
|
||||
return;
|
||||
case SYSCFG_EXTICR1:
|
||||
|
|
|
@ -155,7 +155,7 @@ stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
|
|||
stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
|
||||
|
||||
# stm32f4xx_exti.c
|
||||
stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d"
|
||||
stm32f4xx_exti_set_irq(int irq, int level) "Set EXTI: %d to %d"
|
||||
stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
|
||||
stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
|
||||
|
||||
|
|
|
@ -285,7 +285,7 @@ static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t ps_clk)
|
|||
}
|
||||
|
||||
/**
|
||||
* Compute and set the ouputs clocks periods.
|
||||
* Compute and set the outputs clocks periods.
|
||||
* But do not propagate them further. Connected clocks
|
||||
* will not receive any updates (See zynq_slcr_compute_clocks())
|
||||
*/
|
||||
|
|
|
@ -17,7 +17,7 @@
|
|||
* Notes on coding style
|
||||
* ---------------------
|
||||
* While QEMU coding style prefers lowercase hexadecimals in constants, the
|
||||
* NVMe subsystem use thes format from the NVMe specifications in the comments
|
||||
* NVMe subsystem use this format from the NVMe specifications in the comments
|
||||
* (i.e. 'h' suffix instead of '0x' prefix).
|
||||
*
|
||||
* Usage
|
||||
|
@ -730,7 +730,7 @@ static inline void nvme_sg_unmap(NvmeSg *sg)
|
|||
}
|
||||
|
||||
/*
|
||||
* When metadata is transfered as extended LBAs, the DPTR mapped into `sg`
|
||||
* When metadata is transferred as extended LBAs, the DPTR mapped into `sg`
|
||||
* holds both data and metadata. This function splits the data and metadata
|
||||
* into two separate QSG/IOVs.
|
||||
*/
|
||||
|
@ -7594,7 +7594,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
|
|||
/*
|
||||
* NVM Express v1.3d, Section 4.1 state: "If host software writes
|
||||
* an invalid value to the Submission Queue Tail Doorbell or
|
||||
* Completion Queue Head Doorbell regiter and an Asynchronous Event
|
||||
* Completion Queue Head Doorbell register and an Asynchronous Event
|
||||
* Request command is outstanding, then an asynchronous event is
|
||||
* posted to the Admin Completion Queue with a status code of
|
||||
* Invalid Doorbell Write Value."
|
||||
|
|
|
@ -51,7 +51,7 @@ struct EEPROMState {
|
|||
bool writable;
|
||||
/* cells changed since last START? */
|
||||
bool changed;
|
||||
/* during WRITE, # of address bytes transfered */
|
||||
/* during WRITE, # of address bytes transferred */
|
||||
uint8_t haveaddr;
|
||||
|
||||
uint8_t *mem;
|
||||
|
|
|
@ -877,7 +877,7 @@ static struct {
|
|||
/*
|
||||
* Any sub-page size update to these table MRs will be lost during migration,
|
||||
* as we use aligned size in ram_load_precopy() -> qemu_ram_resize() path.
|
||||
* In order to avoid the inconsistency in sizes save them seperately and
|
||||
* In order to avoid the inconsistency in sizes save them separately and
|
||||
* migrate over in vmstate post_load().
|
||||
*/
|
||||
static void fw_cfg_acpi_mr_save(FWCfgState *s, const char *filename, size_t len)
|
||||
|
|
|
@ -202,7 +202,7 @@ static void exynos4210_rtc_update_freq(Exynos4210RTCState *s,
|
|||
uint32_t freq;
|
||||
|
||||
freq = s->freq;
|
||||
/* set frequncy for time generator */
|
||||
/* set frequency for time generator */
|
||||
s->freq = RTC_BASE_FREQ / (1 << TICCKSEL(reg_value));
|
||||
|
||||
if (freq != s->freq) {
|
||||
|
|
|
@ -114,7 +114,7 @@ static const uint8_t ipr_table[NR_IRQS] = {
|
|||
};
|
||||
|
||||
/*
|
||||
* Level triggerd IRQ list
|
||||
* Level triggered IRQ list
|
||||
* Not listed IRQ is Edge trigger.
|
||||
* See "11.3.1 Interrupt Vector Table" in hardware manual.
|
||||
*/
|
||||
|
|
|
@ -1321,7 +1321,7 @@ again:
|
|||
}
|
||||
trace_lsi_execute_script_io_selected(id,
|
||||
insn & (1 << 3) ? " ATN" : "");
|
||||
/* ??? Linux drivers compain when this is set. Maybe
|
||||
/* ??? Linux drivers complain when this is set. Maybe
|
||||
it only applies in low-level mode (unimplemented).
|
||||
lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
|
||||
s->select_tag = id << 8;
|
||||
|
|
|
@ -65,7 +65,7 @@
|
|||
#define MFI_IQPH 0xc4 /* Inbound queue port (high bytes) */
|
||||
#define MFI_DIAG 0xf8 /* Host diag */
|
||||
#define MFI_SEQ 0xfc /* Sequencer offset */
|
||||
#define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */
|
||||
#define MFI_1078_EIM 0x80000004 /* 1078 enable interrupt mask */
|
||||
#define MFI_RMI 0x2 /* reply message interrupt */
|
||||
#define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */
|
||||
#define MFI_ODC 0x4 /* outbound doorbell change interrupt */
|
||||
|
|
|
@ -113,7 +113,7 @@
|
|||
#define SH7750_TTB SH7750_P4_REG32(SH7750_TTB_REGOFS)
|
||||
#define SH7750_TTB_A7 SH7750_A7_REG32(SH7750_TTB_REGOFS)
|
||||
|
||||
/* TLB exeption address register - TEA */
|
||||
/* TLB exception address register - TEA */
|
||||
#define SH7750_TEA_REGOFS 0x00000c /* offset */
|
||||
#define SH7750_TEA SH7750_P4_REG32(SH7750_TEA_REGOFS)
|
||||
#define SH7750_TEA_A7 SH7750_A7_REG32(SH7750_TEA_REGOFS)
|
||||
|
@ -183,19 +183,19 @@
|
|||
#define SH7750_TRA_IMM 0x000003fd /* Immediate data operand */
|
||||
#define SH7750_TRA_IMM_S 2
|
||||
|
||||
/* Exeption event register - EXPEVT */
|
||||
/* Exception event register - EXPEVT */
|
||||
#define SH7750_EXPEVT_REGOFS 0x000024
|
||||
#define SH7750_EXPEVT SH7750_P4_REG32(SH7750_EXPEVT_REGOFS)
|
||||
#define SH7750_EXPEVT_A7 SH7750_A7_REG32(SH7750_EXPEVT_REGOFS)
|
||||
|
||||
#define SH7750_EXPEVT_EX 0x00000fff /* Exeption code */
|
||||
#define SH7750_EXPEVT_EX 0x00000fff /* Exception code */
|
||||
#define SH7750_EXPEVT_EX_S 0
|
||||
|
||||
/* Interrupt event register */
|
||||
#define SH7750_INTEVT_REGOFS 0x000028
|
||||
#define SH7750_INTEVT SH7750_P4_REG32(SH7750_INTEVT_REGOFS)
|
||||
#define SH7750_INTEVT_A7 SH7750_A7_REG32(SH7750_INTEVT_REGOFS)
|
||||
#define SH7750_INTEVT_EX 0x00000fff /* Exeption code */
|
||||
#define SH7750_INTEVT_EX 0x00000fff /* Exception code */
|
||||
#define SH7750_INTEVT_EX_S 0
|
||||
|
||||
/*
|
||||
|
@ -1274,15 +1274,15 @@
|
|||
/*
|
||||
* User Break Controller registers
|
||||
*/
|
||||
#define SH7750_BARA 0x200000 /* Break address regiser A */
|
||||
#define SH7750_BAMRA 0x200004 /* Break address mask regiser A */
|
||||
#define SH7750_BBRA 0x200008 /* Break bus cycle regiser A */
|
||||
#define SH7750_BARB 0x20000c /* Break address regiser B */
|
||||
#define SH7750_BAMRB 0x200010 /* Break address mask regiser B */
|
||||
#define SH7750_BBRB 0x200014 /* Break bus cycle regiser B */
|
||||
#define SH7750_BASRB 0x000018 /* Break ASID regiser B */
|
||||
#define SH7750_BDRB 0x200018 /* Break data regiser B */
|
||||
#define SH7750_BDMRB 0x20001c /* Break data mask regiser B */
|
||||
#define SH7750_BARA 0x200000 /* Break address register A */
|
||||
#define SH7750_BAMRA 0x200004 /* Break address mask register A */
|
||||
#define SH7750_BBRA 0x200008 /* Break bus cycle register A */
|
||||
#define SH7750_BARB 0x20000c /* Break address register B */
|
||||
#define SH7750_BAMRB 0x200010 /* Break address mask register B */
|
||||
#define SH7750_BBRB 0x200014 /* Break bus cycle register B */
|
||||
#define SH7750_BASRB 0x000018 /* Break ASID register B */
|
||||
#define SH7750_BDRB 0x200018 /* Break data register B */
|
||||
#define SH7750_BDMRB 0x20001c /* Break data mask register B */
|
||||
#define SH7750_BRCR 0x200020 /* Break control register */
|
||||
|
||||
#define SH7750_BRCR_UDBE 0x0001 /* User break debug enable bit */
|
||||
|
|
|
@ -1110,7 +1110,7 @@ void smbios_get_tables(MachineState *ms,
|
|||
dimm_cnt = QEMU_ALIGN_UP(current_machine->ram_size, MAX_DIMM_SZ) / MAX_DIMM_SZ;
|
||||
|
||||
/*
|
||||
* The offset determines if we need to keep additional space betweeen
|
||||
* The offset determines if we need to keep additional space between
|
||||
* table 17 and table 19 header handle numbers so that they do
|
||||
* not overlap. For example, for a VM with larger than 8 TB guest
|
||||
* memory and DIMM like chunks of 16 GiB, the default space between
|
||||
|
|
|
@ -163,7 +163,7 @@
|
|||
FIELD(GQSPI_CNFG, ENDIAN, 26, 1)
|
||||
/* Poll timeout not implemented */
|
||||
FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1)
|
||||
/* QEMU doesnt care about any of these last three */
|
||||
/* QEMU doesn't care about any of these last three */
|
||||
FIELD(GQSPI_CNFG, BR, 3, 3)
|
||||
FIELD(GQSPI_CNFG, CPH, 2, 1)
|
||||
FIELD(GQSPI_CNFG, CPL, 1, 1)
|
||||
|
@ -469,7 +469,7 @@ static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s)
|
|||
|
||||
imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA);
|
||||
if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) {
|
||||
/* immedate transfer */
|
||||
/* immediate transfer */
|
||||
if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) ||
|
||||
ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) {
|
||||
s->regs[R_GQSPI_DATA_STS] = 1;
|
||||
|
@ -768,7 +768,7 @@ static void xilinx_spips_check_zero_pump(XilinxSPIPS *s)
|
|||
*/
|
||||
while (s->regs[R_TRANSFER_SIZE] &&
|
||||
s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) {
|
||||
/* endianess just doesn't matter when zero pumping */
|
||||
/* endianness just doesn't matter when zero pumping */
|
||||
tx_data_bytes(&s->tx_fifo, 0, 4, false);
|
||||
s->regs[R_TRANSFER_SIZE] &= ~0x03ull;
|
||||
s->regs[R_TRANSFER_SIZE] -= 4;
|
||||
|
|
|
@ -837,7 +837,7 @@ static void ospi_do_ind_read(XlnxVersalOspi *s)
|
|||
/* Continue to read flash until we run out of space in sram */
|
||||
while (!ospi_ind_op_completed(op) &&
|
||||
!fifo8_is_full(&s->rx_sram)) {
|
||||
/* Read reqested number of bytes, max bytes limited to size of sram */
|
||||
/* Read requested number of bytes, max bytes limited to size of sram */
|
||||
next_b = ind_op_next_byte(op);
|
||||
end_b = next_b + fifo8_num_free(&s->rx_sram);
|
||||
end_b = MIN(end_b, ind_op_end_byte(op));
|
||||
|
|
|
@ -236,7 +236,7 @@ static void watchdog_hit(void *opaque)
|
|||
{
|
||||
ETRAXTimerState *t = opaque;
|
||||
if (t->wd_hits == 0) {
|
||||
/* real hw gives a single tick before reseting but we are
|
||||
/* real hw gives a single tick before resetting but we are
|
||||
a bit friendlier to compensate for our slower execution. */
|
||||
ptimer_set_count(t->ptimer_wd, 10);
|
||||
ptimer_run(t->ptimer_wd, 1);
|
||||
|
|
|
@ -115,7 +115,7 @@ static int elapsed_time(RTMRState *tmr, int ch, int64_t delta)
|
|||
et = tmr->div_round[ch] / divrate;
|
||||
tmr->div_round[ch] %= divrate;
|
||||
} else {
|
||||
/* disble clock. so no update */
|
||||
/* disable clock. so no update */
|
||||
et = 0;
|
||||
}
|
||||
return et;
|
||||
|
|
|
@ -655,7 +655,7 @@ virtio_crypto_sym_op_helper(VirtIODevice *vdev,
|
|||
op_info->len_to_hash = len_to_hash;
|
||||
op_info->cipher_start_src_offset = cipher_start_src_offset;
|
||||
op_info->len_to_cipher = len_to_cipher;
|
||||
/* Handle the initilization vector */
|
||||
/* Handle the initialization vector */
|
||||
if (op_info->iv_len > 0) {
|
||||
DPRINTF("iv_len=%" PRIu32 "\n", op_info->iv_len);
|
||||
op_info->iv = op_info->data + curr_size;
|
||||
|
@ -1278,7 +1278,7 @@ static void virtio_crypto_instance_init(Object *obj)
|
|||
|
||||
/*
|
||||
* The default config_size is sizeof(struct virtio_crypto_config).
|
||||
* Can be overriden with virtio_crypto_set_config_size.
|
||||
* Can be overridden with virtio_crypto_set_config_size.
|
||||
*/
|
||||
vcrypto->config_size = sizeof(struct virtio_crypto_config);
|
||||
}
|
||||
|
|
|
@ -1119,7 +1119,7 @@ static int virtio_mem_mig_sanity_checks_post_load(void *opaque, int version_id)
|
|||
return -EINVAL;
|
||||
}
|
||||
/*
|
||||
* Note: Preparation for resizeable memory regions. The maximum size
|
||||
* Note: Preparation for resizable memory regions. The maximum size
|
||||
* of the memory region must not change during migration.
|
||||
*/
|
||||
if (tmp->region_size != new_region_size) {
|
||||
|
|
|
@ -2096,7 +2096,7 @@ void virtio_queue_enable(VirtIODevice *vdev, uint32_t queue_index)
|
|||
* being converted to LOG_GUEST_ERROR.
|
||||
*
|
||||
if (!virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) {
|
||||
error_report("queue_enable is only suppported in devices of virtio "
|
||||
error_report("queue_enable is only supported in devices of virtio "
|
||||
"1.0 or later.");
|
||||
}
|
||||
*/
|
||||
|
|
Loading…
Reference in New Issue