Trivial branch pull request 20220401
Fix sh4 linux-user build on Alpine and some trivial updates -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmJGKK0SHGxhdXJlbnRA dml2aWVyLmV1AAoJEPMMOL0/L748eBAP/R4OL8FrmrWjtSPYNpIWUC+pvQpcLLGS JDC8Ty6jYXJ/7vD3AFJyyyfp0DPldX7zhcAZAtWjqdMEHqTm3mYEmmXstHEgy/j3 Kw3zM8r2b3XDV1V4DCqGMOQ8H4j2QxsEti7HeA5NUSHil5FKaRCguwNoh6afriwQ H4KFOiPqcmZEcy6LSGFr5nhhvcrLApJ59aJT8dfzPv86LgP1LUIKNzBfajm/Bzkn vPFhfcnrqlx1hyzQ9CHpqdIAicDxZbkXQyQvSVilncDVnvKEumZ6y4xclF0r68fV KV7yA9KQczdlfC6FvoVR9h5OvghXiKo2u3z5Y/yE6glIRECETEs7sSKv+qTnrXwK 63dMNEEEC5gJ/4sflE6KjL2OdTOPfYuQKgROUgcDmqX7TRvn6+OFBG+mfcgsmr2m 7y18tDxADfLrL71Xcn8pGs34x1WYvE2G+uNW7ax1dmnalYuOzRxbkYSbYi6cbcWx sgyIPkqNgs6maQFZwn3ekpA4I0ApQPzzEk36krKxuG1yWa8eI4f4BIpL+sqYDj/5 cGmjp3idlY+lXWYT0Fijbkv/KunZxIQlkLjj0nTp3fOIuI9aNXlxedXqry/lFr0n Pk0MWNHN2GZKOEyqxsVFsDUS6Fy4qSXfy11TDjAaVAV6xCWhIztWI1YkOOCZi43/ KNUV0DHWSRJb =I8NW -----END PGP SIGNATURE----- Merge tag 'trivial-branch-for-7.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging Trivial branch pull request 20220401 Fix sh4 linux-user build on Alpine and some trivial updates # gpg: Signature made Thu 31 Mar 2022 23:18:21 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * tag 'trivial-branch-for-7.0-pull-request' of https://gitlab.com/laurent_vivier/qemu: tests/lcitool: Do not use a hard-coded /usr/bin/python3 as python interpreter vhost-vdpa: fix typo in a comment target/sh4: Remove old README.sh4 file linux-user/sh4/termbits: Silence warning about TIOCSER_TEMT double definition Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
9b617b1bb4
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@ -299,7 +299,7 @@ static void vhost_vdpa_listener_region_del(MemoryListener *listener,
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memory_region_unref(section->mr);
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}
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/*
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* IOTLB API is used by vhost-vpda which requires incremental updating
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* IOTLB API is used by vhost-vdpa which requires incremental updating
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* of the mapping. So we can not use generic vhost memory listener which
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* depends on the addnop().
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*/
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@ -273,7 +273,7 @@ ebugging only */
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#define TARGET_TIOCSERGETLSR TARGET_IOR('T', 89, unsigned int) /* 0x5459 */ /* Get line sta
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tus register */
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/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
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# define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
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# define TARGET_TIOCSER_TEMT 0x01 /* Transmitter physically empty */
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#define TARGET_TIOCSERGETMULTI TARGET_IOR('T', 90, int) /* 0x545A
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*/ /* Get multiport config */
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#define TARGET_TIOCSERSETMULTI TARGET_IOW('T', 91, int) /* 0x545B
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@ -1,150 +0,0 @@
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qemu target: sh4
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author: Samuel Tardieu <sam@rfc1149.net>
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last modified: Tue Dec 6 07:22:44 CET 2005
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The sh4 target is not ready at all yet for integration in qemu. This
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file describes the current state of implementation.
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Most places requiring attention and/or modification can be detected by
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looking for "XXXXX" or "abort()".
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The sh4 core is located in target/sh4/*, while the 7750 peripheral
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features (IO ports for example) are located in hw/sh7750.[ch]. The
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main board description is in hw/shix.c, and the NAND flash in
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hw/tc58128.[ch].
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All the shortcomings indicated here will eventually be resolved. This
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is a work in progress. Features are added in a semi-random order: if a
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point is blocking to progress on booting the Linux kernel for the shix
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board, it is addressed first; if feedback is necessary and no progress
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can be made on blocking points until it is received, a random feature
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is worked on.
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Goals
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-----
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The primary model being worked on is the soft MMU target to be able to
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emulate the Shix 2.0 board by Alexis Polti, described at
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https://web.archive.org/web/20070917001736/http://perso.enst.fr/~polti/realisations/shix20/
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Ultimately, qemu will be coupled with a system C or a verilog
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simulator to simulate the whole board functionalities.
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A sh4 user-mode has also somewhat started but will be worked on
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afterwards. The goal is to automate tests for GNAT (GNU Ada) compiler
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that I ported recently to the sh4-linux target.
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Registers
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---------
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16 general purpose registers are available at any time. The first 8
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registers are banked and the non-directly visible ones can be accessed
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by privileged instructions. In qemu, we define 24 general purpose
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registers and the code generation use either [0-7]+[8-15] or
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[16-23]+[8-15] depending on the MD and RB flags in the sr
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configuration register.
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Instructions
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------------
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Most sh4 instructions have been implemented. The missing ones at this
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time are:
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- FPU related instructions
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- LDTLB to load a new MMU entry
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- SLEEP to put the processor in sleep mode
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Most instructions could be optimized a lot. This will be worked on
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after the current model is fully functional unless debugging
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convenience requires that it is done early.
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Many instructions did not have a chance to be tested yet. The plan is
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to implement unit and regression testing of those in the future.
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MMU
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---
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The MMU is implemented in the sh4 core. MMU management has not been
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tested at all yet. In the sh7750, it can be manipulated through memory
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mapped registers and this part has not yet been implemented.
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Exceptions
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----------
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Exceptions are implemented as described in the sh4 reference manual
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but have not been tested yet. They do not use qemu EXCP_ features
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yet.
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IRQ
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---
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IRQ are not implemented yet.
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Peripheral features
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-------------------
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+ Serial ports
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Configuration and use of the first serial port (SCI) without
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interrupts is supported. Input has not yet been tested.
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Configuration of the second serial port (SCIF) is supported. FIFO
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handling infrastructure has been started but is not completed yet.
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+ GPIO ports
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GPIO ports have been implemented. A registration function allows
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external modules to register interest in some port changes (see
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hw/tc58128.[ch] for an example) and will be called back. Interrupt
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generation is not yet supported but some infrastructure is in place
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for this purpose. Note that in the current model a peripheral module
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cannot directly simulate a H->L->H input port transition and have an
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interrupt generated on the low level.
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+ TC58128 NAND flash
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TC58128 NAND flash is partially implemented through GPIO ports. It
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supports reading from flash.
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GDB
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---
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GDB remote target support has been implemented and lightly tested.
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Files
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-----
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File names are hardcoded at this time. The bootloader must be stored in
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shix_bios.bin in the current directory. The initial Linux image must
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be stored in shix_linux_nand.bin in the current directory in NAND
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format. Test files can be obtained from
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http://perso.enst.fr/~polti/robot/ as well as the various datasheets I
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use.
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qemu disk parameter on the command line is unused. You can supply any
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existing image and it will be ignored. As the goal is to simulate an
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embedded target, it is not clear how this parameter will be handled in
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the future.
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To build an ELF kernel image from the NAND image, 16 bytes have to be
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stripped off the end of every 528 bytes, keeping only 512 of them. The
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following Python code snippet does it:
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#! /usr/bin/python
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def denand (infd, outfd):
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while True:
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d = infd.read (528)
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if not d: return
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outfd.write (d[:512])
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if __name__ == '__main__':
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import sys
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denand (open (sys.argv[1], 'rb'),
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open (sys.argv[2], 'wb'))
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Style isssues
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-------------
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There is currently a mix between my style (space before opening
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parenthesis) and qemu style. This will be resolved before final
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integration is proposed.
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@ -14,4 +14,4 @@ lcitool-help: lcitool
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lcitool-refresh:
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$(call quiet-command, cd $(SRC_PATH) && git submodule update --init tests/lcitool/libvirt-ci)
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$(call quiet-command, $(LCITOOL_REFRESH))
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$(call quiet-command, $(PYTHON) $(LCITOOL_REFRESH))
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@ -1,4 +1,4 @@
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#!/usr/bin/python3
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#!/usr/bin/env python3
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#
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# Re-generate container recipes
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#
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