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target/loongarch: Add floating point comparison instruction translation 

This includes:
- FCMP.cond.{S/D}

Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-12-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Song Gao 2022-06-06 20:43:01 +08:00 committed by Richard Henderson
parent d578ca6cbb
commit 9b7410763a
6 changed files with 139 additions and 0 deletions
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60
target/loongarch/fpu_helper.c
View File

@ -401,3 +401,63 @@ uint64_t helper_fmuladd_d(CPULoongArchState *env, uint64_t fj,
update_fcsr0(env, GETPC());
return fd;
}
static uint64_t fcmp_common(CPULoongArchState *env, FloatRelation cmp,
uint32_t flags)
{
bool ret;
switch (cmp) {
case float_relation_less:
ret = (flags & FCMP_LT);
break;
case float_relation_equal:
ret = (flags & FCMP_EQ);
break;
case float_relation_greater:
ret = (flags & FCMP_GT);
break;
case float_relation_unordered:
ret = (flags & FCMP_UN);
break;
default:
g_assert_not_reached();
}
update_fcsr0(env, GETPC());
return ret;
}
/* fcmp_cXXX_s */
uint64_t helper_fcmp_c_s(CPULoongArchState *env, uint64_t fj,
uint64_t fk, uint32_t flags)
{
FloatRelation cmp = float32_compare_quiet((uint32_t)fj,
(uint32_t)fk, &env->fp_status);
return fcmp_common(env, cmp, flags);
}
/* fcmp_sXXX_s */
uint64_t helper_fcmp_s_s(CPULoongArchState *env, uint64_t fj,
uint64_t fk, uint32_t flags)
{
FloatRelation cmp = float32_compare((uint32_t)fj,
(uint32_t)fk, &env->fp_status);
return fcmp_common(env, cmp, flags);
}
/* fcmp_cXXX_d */
uint64_t helper_fcmp_c_d(CPULoongArchState *env, uint64_t fj,
uint64_t fk, uint32_t flags)
{
FloatRelation cmp = float64_compare_quiet(fj, fk, &env->fp_status);
return fcmp_common(env, cmp, flags);
}
/* fcmp_sXXX_d */
uint64_t helper_fcmp_s_d(CPULoongArchState *env, uint64_t fj,
uint64_t fk, uint32_t flags)
{
FloatRelation cmp = float64_compare(fj, fk, &env->fp_status);
return fcmp_common(env, cmp, flags);
}

9
target/loongarch/helper.h
View File

@ -52,3 +52,12 @@ DEF_HELPER_FLAGS_2(frecip_d, TCG_CALL_NO_WG, i64, env, i64)
DEF_HELPER_FLAGS_2(fclass_s, TCG_CALL_NO_RWG_SE, i64, env, i64)
DEF_HELPER_FLAGS_2(fclass_d, TCG_CALL_NO_RWG_SE, i64, env, i64)
/* fcmp.cXXX.s */
DEF_HELPER_4(fcmp_c_s, i64, env, i64, i64, i32)
/* fcmp.sXXX.s */
DEF_HELPER_4(fcmp_s_s, i64, env, i64, i64, i32)
/* fcmp.cXXX.d */
DEF_HELPER_4(fcmp_c_d, i64, env, i64, i64, i32)
/* fcmp.sXXX.d */
DEF_HELPER_4(fcmp_s_d, i64, env, i64, i64, i32)

56
target/loongarch/insn_trans/trans_fcmp.c.inc Normal file
View File

@ -0,0 +1,56 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2021 Loongson Technology Corporation Limited
*/
/* bit0(signaling/quiet) bit1(lt) bit2(eq) bit3(un) bit4(neq) */
static uint32_t get_fcmp_flags(int cond)
{
uint32_t flags = 0;
if (cond & 0x1) {
flags |= FCMP_LT;
}
if (cond & 0x2) {
flags |= FCMP_EQ;
}
if (cond & 0x4) {
flags |= FCMP_UN;
}
if (cond & 0x8) {
flags |= FCMP_GT | FCMP_LT;
}
return flags;
}
static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
{
TCGv var = tcg_temp_new();
uint32_t flags;
void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
fn = (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s);
flags = get_fcmp_flags(a->fcond >> 1);
fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flags));
tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd]));
tcg_temp_free(var);
return true;
}
static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)
{
TCGv var = tcg_temp_new();
uint32_t flags;
void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
fn = (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d);
flags = get_fcmp_flags(a->fcond >> 1);
fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flags));
tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd]));
tcg_temp_free(var);
return true;
}

8
target/loongarch/insns.decode
View File

@ -26,6 +26,7 @@
&ff fd fj
&fff fd fj fk
&ffff fd fj fk fa
&cff_fcond cd fj fk fcond
#
# Formats
@ -50,6 +51,7 @@
@ff .... ........ ..... ..... fj:5 fd:5 &ff
@fff .... ........ ..... fk:5 fj:5 fd:5 &fff
@ffff .... ........ fa:5 fk:5 fj:5 fd:5 &ffff
@cff_fcond .... ........ fcond:5 fk:5 fj:5 .. cd:3 &cff_fcond
#
# Fixed point arithmetic operation instruction
@ -308,3 +310,9 @@ fcopysign_s 0000 00010001 00101 ..... ..... ..... @fff
fcopysign_d 0000 00010001 00110 ..... ..... ..... @fff
fclass_s 0000 00010001 01000 01101 ..... ..... @ff
fclass_d 0000 00010001 01000 01110 ..... ..... @ff
#
# Floating point compare instruction
#
fcmp_cond_s 0000 11000001 ..... ..... ..... 00 ... @cff_fcond
fcmp_cond_d 0000 11000010 ..... ..... ..... 00 ... @cff_fcond

5
target/loongarch/internals.h
View File

@ -8,6 +8,11 @@
#ifndef LOONGARCH_INTERNALS_H
#define LOONGARCH_INTERNALS_H
#define FCMP_LT 0b0001 /* fp0 < fp1 */
#define FCMP_EQ 0b0010 /* fp0 = fp1 */
#define FCMP_UN 0b0100 /* unordered */
#define FCMP_GT 0b1000 /* fp0 > fp1 */
void loongarch_translate_init(void);
void loongarch_cpu_dump_state(CPUState *cpu, FILE *f, int flags);

1
target/loongarch/translate.c
View File

@ -167,6 +167,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
#include "insn_trans/trans_atomic.c.inc"
#include "insn_trans/trans_extra.c.inc"
#include "insn_trans/trans_farith.c.inc"
#include "insn_trans/trans_fcmp.c.inc"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{