i440fx-test: add test to compare default register values
This test compares all of the default register values against the spec. It turns out we deviate in quite a few places. These places are really only visible to the BIOS though which is why this hasn't created any problems. The deviation actually happens in the core PCI layer so I suspect it's not a simple fix if we really care to fix it. For now, just disable the affected checks. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1366123521-4330-6-git-send-email-aliguori@us.ibm.com
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@ -54,6 +54,7 @@ gcov-files-i386-y = hw/fdc.c
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check-qtest-i386-y += tests/hd-geo-test$(EXESUF)
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gcov-files-i386-y += hw/hd-geometry.c
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check-qtest-i386-y += tests/rtc-test$(EXESUF)
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check-qtest-i386-y += tests/i440fx-test$(EXESUF)
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check-qtest-x86_64-y = $(check-qtest-i386-y)
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gcov-files-i386-y += i386-softmmu/hw/mc146818rtc.c
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gcov-files-x86_64-y = $(subst i386-softmmu/,x86_64-softmmu/,$(gcov-files-i386-y))
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@ -125,6 +126,7 @@ tests/m48t59-test$(EXESUF): tests/m48t59-test.o
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tests/fdc-test$(EXESUF): tests/fdc-test.o
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tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
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tests/tmp105-test$(EXESUF): tests/tmp105-test.o
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tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
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# QTest rules
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@ -0,0 +1,148 @@
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/*
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* qtest I440FX test case
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*
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* Copyright IBM, Corp. 2012-2013
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "libqos/pci.h"
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#include "libqos/pci-pc.h"
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#include "libqtest.h"
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#include "hw/pci/pci_regs.h"
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#include <glib.h>
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#include <stdio.h>
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#define BROKEN 1
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typedef struct TestData
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{
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int num_cpus;
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QPCIBus *bus;
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} TestData;
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static void test_i440fx_defaults(gconstpointer opaque)
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{
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const TestData *s = opaque;
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QPCIDevice *dev;
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uint32_t value;
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dev = qpci_device_find(s->bus, QPCI_DEVFN(0, 0));
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g_assert(dev != NULL);
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/* 3.2.2 */
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g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086);
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/* 3.2.3 */
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g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237);
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#ifndef BROKEN
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/* 3.2.4 */
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g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006);
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/* 3.2.5 */
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g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280);
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#endif
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/* 3.2.7 */
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g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00);
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g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600);
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/* 3.2.8 */
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g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00);
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/* 3.2.9 */
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g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00);
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/* 3.2.10 */
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g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00);
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/* 3.2.11 */
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value = qpci_config_readw(dev, 0x50); /* PMCCFG */
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if (s->num_cpus == 1) { /* WPE */
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g_assert(!(value & (1 << 15)));
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} else {
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g_assert((value & (1 << 15)));
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}
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g_assert(!(value & (1 << 6))); /* EPTE */
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/* 3.2.12 */
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g_assert_cmpint(qpci_config_readb(dev, 0x52), ==, 0x00); /* DETURBO */
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/* 3.2.13 */
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#ifndef BROKEN
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g_assert_cmpint(qpci_config_readb(dev, 0x53), ==, 0x80); /* DBC */
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#endif
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/* 3.2.14 */
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g_assert_cmpint(qpci_config_readb(dev, 0x54), ==, 0x00); /* AXC */
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/* 3.2.15 */
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g_assert_cmpint(qpci_config_readw(dev, 0x55), ==, 0x0000); /* DRT */
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#ifndef BROKEN
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/* 3.2.16 */
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g_assert_cmpint(qpci_config_readb(dev, 0x57), ==, 0x01); /* DRAMC */
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/* 3.2.17 */
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g_assert_cmpint(qpci_config_readb(dev, 0x58), ==, 0x10); /* DRAMT */
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#endif
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/* 3.2.18 */
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g_assert_cmpint(qpci_config_readb(dev, 0x59), ==, 0x00); /* PAM0 */
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g_assert_cmpint(qpci_config_readb(dev, 0x5A), ==, 0x00); /* PAM1 */
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g_assert_cmpint(qpci_config_readb(dev, 0x5B), ==, 0x00); /* PAM2 */
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g_assert_cmpint(qpci_config_readb(dev, 0x5C), ==, 0x00); /* PAM3 */
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g_assert_cmpint(qpci_config_readb(dev, 0x5D), ==, 0x00); /* PAM4 */
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g_assert_cmpint(qpci_config_readb(dev, 0x5E), ==, 0x00); /* PAM5 */
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g_assert_cmpint(qpci_config_readb(dev, 0x5F), ==, 0x00); /* PAM6 */
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#ifndef BROKEN
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/* 3.2.19 */
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g_assert_cmpint(qpci_config_readb(dev, 0x60), ==, 0x01); /* DRB0 */
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g_assert_cmpint(qpci_config_readb(dev, 0x61), ==, 0x01); /* DRB1 */
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g_assert_cmpint(qpci_config_readb(dev, 0x62), ==, 0x01); /* DRB2 */
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g_assert_cmpint(qpci_config_readb(dev, 0x63), ==, 0x01); /* DRB3 */
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g_assert_cmpint(qpci_config_readb(dev, 0x64), ==, 0x01); /* DRB4 */
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g_assert_cmpint(qpci_config_readb(dev, 0x65), ==, 0x01); /* DRB5 */
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g_assert_cmpint(qpci_config_readb(dev, 0x66), ==, 0x01); /* DRB6 */
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g_assert_cmpint(qpci_config_readb(dev, 0x67), ==, 0x01); /* DRB7 */
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#endif
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/* 3.2.20 */
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g_assert_cmpint(qpci_config_readb(dev, 0x68), ==, 0x00); /* FDHC */
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/* 3.2.21 */
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g_assert_cmpint(qpci_config_readb(dev, 0x70), ==, 0x00); /* MTT */
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#ifndef BROKEN
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/* 3.2.22 */
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g_assert_cmpint(qpci_config_readb(dev, 0x71), ==, 0x10); /* CLT */
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#endif
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/* 3.2.23 */
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g_assert_cmpint(qpci_config_readb(dev, 0x72), ==, 0x02); /* SMRAM */
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/* 3.2.24 */
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g_assert_cmpint(qpci_config_readb(dev, 0x90), ==, 0x00); /* ERRCMD */
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/* 3.2.25 */
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g_assert_cmpint(qpci_config_readb(dev, 0x91), ==, 0x00); /* ERRSTS */
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/* 3.2.26 */
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g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */
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}
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int main(int argc, char **argv)
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{
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QTestState *s;
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TestData data;
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char *cmdline;
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int ret;
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g_test_init(&argc, &argv, NULL);
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data.num_cpus = 1;
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cmdline = g_strdup_printf("-display none -smp %d", data.num_cpus);
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s = qtest_start(cmdline);
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g_free(cmdline);
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data.bus = qpci_init_pc();
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g_test_add_data_func("/i440fx/defaults", &data, test_i440fx_defaults);
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ret = g_test_run();
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if (s) {
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qtest_quit(s);
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}
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return ret;
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}
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