hw/arm/smmuv3: Implement translate callback
This patch implements the IOMMU Memory Region translate() callback. Most of the code relates to the translation configuration decoding and check (STE, CD). Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Message-id: 1524665762-31355-10-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Eric Auger
Peter Maydell
parent
bb981004ea
commit
9bde7f0674
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@ -458,4 +458,164 @@ typedef struct SMMUEventInfo {
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void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event);
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/* Configuration Data */
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/* STE Level 1 Descriptor */
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typedef struct STEDesc {
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uint32_t word[2];
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} STEDesc;
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/* CD Level 1 Descriptor */
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typedef struct CDDesc {
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uint32_t word[2];
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} CDDesc;
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/* Stream Table Entry(STE) */
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typedef struct STE {
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uint32_t word[16];
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} STE;
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/* Context Descriptor(CD) */
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typedef struct CD {
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uint32_t word[16];
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} CD;
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/* STE fields */
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#define STE_VALID(x) extract32((x)->word[0], 0, 1)
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#define STE_CONFIG(x) extract32((x)->word[0], 1, 3)
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#define STE_CFG_S1_ENABLED(config) (config & 0x1)
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#define STE_CFG_S2_ENABLED(config) (config & 0x2)
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#define STE_CFG_ABORT(config) (!(config & 0x4))
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#define STE_CFG_BYPASS(config) (config == 0x4)
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#define STE_S1FMT(x) extract32((x)->word[0], 4 , 2)
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#define STE_S1CDMAX(x) extract32((x)->word[1], 27, 5)
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#define STE_S1STALLD(x) extract32((x)->word[2], 27, 1)
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#define STE_EATS(x) extract32((x)->word[2], 28, 2)
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#define STE_STRW(x) extract32((x)->word[2], 30, 2)
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#define STE_S2VMID(x) extract32((x)->word[4], 0 , 16)
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#define STE_S2T0SZ(x) extract32((x)->word[5], 0 , 6)
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#define STE_S2SL0(x) extract32((x)->word[5], 6 , 2)
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#define STE_S2TG(x) extract32((x)->word[5], 14, 2)
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#define STE_S2PS(x) extract32((x)->word[5], 16, 3)
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#define STE_S2AA64(x) extract32((x)->word[5], 19, 1)
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#define STE_S2HD(x) extract32((x)->word[5], 24, 1)
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#define STE_S2HA(x) extract32((x)->word[5], 25, 1)
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#define STE_S2S(x) extract32((x)->word[5], 26, 1)
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#define STE_CTXPTR(x) \
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({ \
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unsigned long addr; \
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addr = (uint64_t)extract32((x)->word[1], 0, 16) << 32; \
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addr |= (uint64_t)((x)->word[0] & 0xffffffc0); \
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addr; \
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})
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#define STE_S2TTB(x) \
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({ \
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unsigned long addr; \
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addr = (uint64_t)extract32((x)->word[7], 0, 16) << 32; \
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addr |= (uint64_t)((x)->word[6] & 0xfffffff0); \
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addr; \
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})
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static inline int oas2bits(int oas_field)
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{
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switch (oas_field) {
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case 0:
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return 32;
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case 1:
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return 36;
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case 2:
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return 40;
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case 3:
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return 42;
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case 4:
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return 44;
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case 5:
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return 48;
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}
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return -1;
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}
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static inline int pa_range(STE *ste)
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{
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int oas_field = MIN(STE_S2PS(ste), SMMU_IDR5_OAS);
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if (!STE_S2AA64(ste)) {
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return 40;
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}
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return oas2bits(oas_field);
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}
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#define MAX_PA(ste) ((1 << pa_range(ste)) - 1)
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/* CD fields */
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#define CD_VALID(x) extract32((x)->word[0], 30, 1)
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#define CD_ASID(x) extract32((x)->word[1], 16, 16)
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#define CD_TTB(x, sel) \
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({ \
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uint64_t hi, lo; \
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hi = extract32((x)->word[(sel) * 2 + 3], 0, 19); \
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hi <<= 32; \
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lo = (x)->word[(sel) * 2 + 2] & ~0xfULL; \
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hi | lo; \
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})
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#define CD_TSZ(x, sel) extract32((x)->word[0], (16 * (sel)) + 0, 6)
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#define CD_TG(x, sel) extract32((x)->word[0], (16 * (sel)) + 6, 2)
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#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1)
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#define CD_ENDI(x) extract32((x)->word[0], 15, 1)
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#define CD_IPS(x) extract32((x)->word[1], 0 , 3)
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#define CD_TBI(x) extract32((x)->word[1], 6 , 2)
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#define CD_HD(x) extract32((x)->word[1], 10 , 1)
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#define CD_HA(x) extract32((x)->word[1], 11 , 1)
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#define CD_S(x) extract32((x)->word[1], 12, 1)
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#define CD_R(x) extract32((x)->word[1], 13, 1)
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#define CD_A(x) extract32((x)->word[1], 14, 1)
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#define CD_AARCH64(x) extract32((x)->word[1], 9 , 1)
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#define CDM_VALID(x) ((x)->word[0] & 0x1)
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static inline int is_cd_valid(SMMUv3State *s, STE *ste, CD *cd)
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{
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return CD_VALID(cd);
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}
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/**
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* tg2granule - Decodes the CD translation granule size field according
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* to the ttbr in use
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* @bits: TG0/1 fields
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* @ttbr: ttbr index in use
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*/
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static inline int tg2granule(int bits, int ttbr)
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{
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switch (bits) {
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case 0:
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return ttbr ? 0 : 12;
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case 1:
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return ttbr ? 14 : 16;
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case 2:
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return ttbr ? 12 : 14;
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case 3:
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return ttbr ? 16 : 0;
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default:
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return 0;
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}
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}
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static inline uint64_t l1std_l2ptr(STEDesc *desc)
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{
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uint64_t hi, lo;
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hi = desc->word[1];
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lo = desc->word[0] & ~0x1fULL;
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return hi << 32 | lo;
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}
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#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 4))
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#endif
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358
hw/arm/smmuv3.c
358
hw/arm/smmuv3.c
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@ -271,6 +271,361 @@ static void smmuv3_init_regs(SMMUv3State *s)
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s->sid_split = 0;
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}
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static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
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SMMUEventInfo *event)
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{
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int ret;
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trace_smmuv3_get_ste(addr);
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/* TODO: guarantee 64-bit single-copy atomicity */
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ret = dma_memory_read(&address_space_memory, addr,
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(void *)buf, sizeof(*buf));
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if (ret != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Cannot fetch pte at address=0x%"PRIx64"\n", addr);
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event->type = SMMU_EVT_F_STE_FETCH;
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event->u.f_ste_fetch.addr = addr;
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return -EINVAL;
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}
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return 0;
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}
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/* @ssid > 0 not supported yet */
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static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
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CD *buf, SMMUEventInfo *event)
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{
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dma_addr_t addr = STE_CTXPTR(ste);
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int ret;
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trace_smmuv3_get_cd(addr);
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/* TODO: guarantee 64-bit single-copy atomicity */
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ret = dma_memory_read(&address_space_memory, addr,
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(void *)buf, sizeof(*buf));
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if (ret != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Cannot fetch pte at address=0x%"PRIx64"\n", addr);
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event->type = SMMU_EVT_F_CD_FETCH;
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event->u.f_ste_fetch.addr = addr;
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return -EINVAL;
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}
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return 0;
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}
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/* Returns <0 if the caller has no need to continue the translation */
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static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
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STE *ste, SMMUEventInfo *event)
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{
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uint32_t config;
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int ret = -EINVAL;
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if (!STE_VALID(ste)) {
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goto bad_ste;
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}
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config = STE_CONFIG(ste);
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if (STE_CFG_ABORT(config)) {
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cfg->aborted = true; /* abort but don't record any event */
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return ret;
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}
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if (STE_CFG_BYPASS(config)) {
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cfg->bypassed = true;
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return ret;
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}
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if (STE_CFG_S2_ENABLED(config)) {
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qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n");
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goto bad_ste;
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}
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if (STE_S1CDMAX(ste) != 0) {
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qemu_log_mask(LOG_UNIMP,
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"SMMUv3 does not support multiple context descriptors yet\n");
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goto bad_ste;
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}
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if (STE_S1STALLD(ste)) {
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qemu_log_mask(LOG_UNIMP,
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"SMMUv3 S1 stalling fault model not allowed yet\n");
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goto bad_ste;
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}
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return 0;
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bad_ste:
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event->type = SMMU_EVT_C_BAD_STE;
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return -EINVAL;
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}
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/**
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* smmu_find_ste - Return the stream table entry associated
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* to the sid
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*
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* @s: smmuv3 handle
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* @sid: stream ID
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* @ste: returned stream table entry
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* @event: handle to an event info
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*
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* Supports linear and 2-level stream table
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* Return 0 on success, -EINVAL otherwise
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*/
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static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste,
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SMMUEventInfo *event)
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{
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dma_addr_t addr;
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int ret;
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trace_smmuv3_find_ste(sid, s->features, s->sid_split);
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/* Check SID range */
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if (sid > (1 << SMMU_IDR1_SIDSIZE)) {
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event->type = SMMU_EVT_C_BAD_STREAMID;
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return -EINVAL;
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}
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if (s->features & SMMU_FEATURE_2LVL_STE) {
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int l1_ste_offset, l2_ste_offset, max_l2_ste, span;
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dma_addr_t strtab_base, l1ptr, l2ptr;
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STEDesc l1std;
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strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK;
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l1_ste_offset = sid >> s->sid_split;
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l2_ste_offset = sid & ((1 << s->sid_split) - 1);
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l1ptr = (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std));
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/* TODO: guarantee 64-bit single-copy atomicity */
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ret = dma_memory_read(&address_space_memory, l1ptr,
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(uint8_t *)&l1std, sizeof(l1std));
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if (ret != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Could not read L1PTR at 0X%"PRIx64"\n", l1ptr);
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event->type = SMMU_EVT_F_STE_FETCH;
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event->u.f_ste_fetch.addr = l1ptr;
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return -EINVAL;
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}
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span = L1STD_SPAN(&l1std);
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if (!span) {
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/* l2ptr is not valid */
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qemu_log_mask(LOG_GUEST_ERROR,
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"invalid sid=%d (L1STD span=0)\n", sid);
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event->type = SMMU_EVT_C_BAD_STREAMID;
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return -EINVAL;
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}
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max_l2_ste = (1 << span) - 1;
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l2ptr = l1std_l2ptr(&l1std);
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trace_smmuv3_find_ste_2lvl(s->strtab_base, l1ptr, l1_ste_offset,
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l2ptr, l2_ste_offset, max_l2_ste);
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if (l2_ste_offset > max_l2_ste) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"l2_ste_offset=%d > max_l2_ste=%d\n",
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l2_ste_offset, max_l2_ste);
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event->type = SMMU_EVT_C_BAD_STE;
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return -EINVAL;
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}
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addr = l2ptr + l2_ste_offset * sizeof(*ste);
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} else {
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addr = s->strtab_base + sid * sizeof(*ste);
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}
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if (smmu_get_ste(s, addr, ste, event)) {
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return -EINVAL;
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}
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return 0;
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}
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static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
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{
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int ret = -EINVAL;
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int i;
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if (!CD_VALID(cd) || !CD_AARCH64(cd)) {
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goto bad_cd;
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}
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if (!CD_A(cd)) {
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goto bad_cd; /* SMMU_IDR0.TERM_MODEL == 1 */
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}
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if (CD_S(cd)) {
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goto bad_cd; /* !STE_SECURE && SMMU_IDR0.STALL_MODEL == 1 */
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}
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if (CD_HA(cd) || CD_HD(cd)) {
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goto bad_cd; /* HTTU = 0 */
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}
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/* we support only those at the moment */
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cfg->aa64 = true;
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cfg->stage = 1;
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cfg->oas = oas2bits(CD_IPS(cd));
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cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
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cfg->tbi = CD_TBI(cd);
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cfg->asid = CD_ASID(cd);
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trace_smmuv3_decode_cd(cfg->oas);
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/* decode data dependent on TT */
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for (i = 0; i <= 1; i++) {
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int tg, tsz;
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SMMUTransTableInfo *tt = &cfg->tt[i];
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cfg->tt[i].disabled = CD_EPD(cd, i);
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if (cfg->tt[i].disabled) {
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continue;
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}
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tsz = CD_TSZ(cd, i);
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if (tsz < 16 || tsz > 39) {
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goto bad_cd;
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}
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tg = CD_TG(cd, i);
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tt->granule_sz = tg2granule(tg, i);
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if ((tt->granule_sz != 12 && tt->granule_sz != 16) || CD_ENDI(cd)) {
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goto bad_cd;
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}
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tt->tsz = tsz;
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tt->ttb = CD_TTB(cd, i);
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if (tt->ttb & ~(MAKE_64BIT_MASK(0, cfg->oas))) {
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goto bad_cd;
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}
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trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz);
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}
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event->record_trans_faults = CD_R(cd);
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return 0;
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bad_cd:
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event->type = SMMU_EVT_C_BAD_CD;
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return ret;
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}
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/**
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* smmuv3_decode_config - Prepare the translation configuration
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* for the @mr iommu region
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* @mr: iommu memory region the translation config must be prepared for
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* @cfg: output translation configuration which is populated through
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* the different configuration decoding steps
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* @event: must be zero'ed by the caller
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*
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* return < 0 if the translation needs to be aborted (@event is filled
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* accordingly). Return 0 otherwise.
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*/
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static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg,
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SMMUEventInfo *event)
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{
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SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
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uint32_t sid = smmu_get_sid(sdev);
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SMMUv3State *s = sdev->smmu;
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int ret = -EINVAL;
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STE ste;
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CD cd;
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if (smmu_find_ste(s, sid, &ste, event)) {
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return ret;
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}
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if (decode_ste(s, cfg, &ste, event)) {
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return ret;
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}
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if (smmu_get_cd(s, &ste, 0 /* ssid */, &cd, event)) {
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return ret;
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}
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return decode_cd(cfg, &cd, event);
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}
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static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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IOMMUAccessFlags flag)
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{
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SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
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SMMUv3State *s = sdev->smmu;
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uint32_t sid = smmu_get_sid(sdev);
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SMMUEventInfo event = {.type = SMMU_EVT_OK, .sid = sid};
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SMMUPTWEventInfo ptw_info = {};
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SMMUTransCfg cfg = {};
|
||||
IOMMUTLBEntry entry = {
|
||||
.target_as = &address_space_memory,
|
||||
.iova = addr,
|
||||
.translated_addr = addr,
|
||||
.addr_mask = ~(hwaddr)0,
|
||||
.perm = IOMMU_NONE,
|
||||
};
|
||||
int ret = 0;
|
||||
|
||||
if (!smmu_enabled(s)) {
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = smmuv3_decode_config(mr, &cfg, &event);
|
||||
if (ret) {
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (cfg.aborted) {
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = smmu_ptw(&cfg, addr, flag, &entry, &ptw_info);
|
||||
if (ret) {
|
||||
switch (ptw_info.type) {
|
||||
case SMMU_PTW_ERR_WALK_EABT:
|
||||
event.type = SMMU_EVT_F_WALK_EABT;
|
||||
event.u.f_walk_eabt.addr = addr;
|
||||
event.u.f_walk_eabt.rnw = flag & 0x1;
|
||||
event.u.f_walk_eabt.class = 0x1;
|
||||
event.u.f_walk_eabt.addr2 = ptw_info.addr;
|
||||
break;
|
||||
case SMMU_PTW_ERR_TRANSLATION:
|
||||
if (event.record_trans_faults) {
|
||||
event.type = SMMU_EVT_F_TRANSLATION;
|
||||
event.u.f_translation.addr = addr;
|
||||
event.u.f_translation.rnw = flag & 0x1;
|
||||
}
|
||||
break;
|
||||
case SMMU_PTW_ERR_ADDR_SIZE:
|
||||
if (event.record_trans_faults) {
|
||||
event.type = SMMU_EVT_F_ADDR_SIZE;
|
||||
event.u.f_addr_size.addr = addr;
|
||||
event.u.f_addr_size.rnw = flag & 0x1;
|
||||
}
|
||||
break;
|
||||
case SMMU_PTW_ERR_ACCESS:
|
||||
if (event.record_trans_faults) {
|
||||
event.type = SMMU_EVT_F_ACCESS;
|
||||
event.u.f_access.addr = addr;
|
||||
event.u.f_access.rnw = flag & 0x1;
|
||||
}
|
||||
break;
|
||||
case SMMU_PTW_ERR_PERMISSION:
|
||||
if (event.record_trans_faults) {
|
||||
event.type = SMMU_EVT_F_PERMISSION;
|
||||
event.u.f_permission.addr = addr;
|
||||
event.u.f_permission.rnw = flag & 0x1;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
}
|
||||
}
|
||||
out:
|
||||
if (ret) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"%s translation failed for iova=0x%"PRIx64"(%d)\n",
|
||||
mr->parent_obj.name, addr, ret);
|
||||
entry.perm = IOMMU_NONE;
|
||||
smmuv3_record_event(s, &event);
|
||||
} else if (!cfg.aborted) {
|
||||
entry.perm = flag;
|
||||
trace_smmuv3_translate(mr->parent_obj.name, sid, addr,
|
||||
entry.translated_addr, entry.perm);
|
||||
}
|
||||
|
||||
return entry;
|
||||
}
|
||||
|
||||
static int smmuv3_cmdq_consume(SMMUv3State *s)
|
||||
{
|
||||
SMMUCmdError cmd_error = SMMU_CERROR_NONE;
|
||||
|
|
@ -795,6 +1150,9 @@ static void smmuv3_class_init(ObjectClass *klass, void *data)
|
|||
static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass,
|
||||
void *data)
|
||||
{
|
||||
IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
|
||||
|
||||
imrc->translate = smmuv3_translate;
|
||||
}
|
||||
|
||||
static const TypeInfo smmuv3_type_info = {
|
||||
|
|
|
|||
|
|
@ -30,3 +30,12 @@ smmuv3_write_mmio_idr(uint64_t addr, uint64_t val) "write to RO/Unimpl reg 0x%"P
|
|||
smmuv3_write_mmio_evtq_cons_bef_clear(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "Before clearing interrupt prod:0x%x cons:0x%x prod.w:%d cons.w:%d"
|
||||
smmuv3_write_mmio_evtq_cons_after_clear(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "after clearing interrupt prod:0x%x cons:0x%x prod.w:%d cons.w:%d"
|
||||
smmuv3_record_event(const char *type, uint32_t sid) "%s sid=%d"
|
||||
smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "SID:0x%x features:0x%x, sid_split:0x%x"
|
||||
smmuv3_find_ste_2lvl(uint64_t strtab_base, uint64_t l1ptr, int l1_ste_offset, uint64_t l2ptr, int l2_ste_offset, int max_l2_ste) "strtab_base:0x%"PRIx64" l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64" l2_off:0x%x max_l2_ste:%d"
|
||||
smmuv3_get_ste(uint64_t addr) "STE addr: 0x%"PRIx64
|
||||
smmuv3_translate_bypass(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=%d bypass iova:0x%"PRIx64" is_write=%d"
|
||||
smmuv3_translate_in(uint16_t sid, int pci_bus_num, uint64_t strtab_base) "SID:0x%x bus:%d strtab_base:0x%"PRIx64
|
||||
smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64
|
||||
smmuv3_translate(const char *n, uint16_t sid, uint64_t iova, uint64_t translated, int perm) "%s sid=%d iova=0x%"PRIx64" translated=0x%"PRIx64" perm=0x%x"
|
||||
smmuv3_decode_cd(uint32_t oas) "oas=%d"
|
||||
smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d"
|
||||
|
|
|
|||
Loading…
Reference in New Issue