OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

MIPS patches queue 

Hardware emulation:
 - Generate FDT blob for Boston machine (Jiaxun)
 - VIA chipset cleanups (Zoltan)
 
 TCG:
 - Use tcg_constant() in Compact branch and MSA opcodes
 - Restrict nanoMIPS DSP MULT[U] opcode accumulator to Rel6
 - Fix DEXTRV_S.H DSP opcode
 - Remove unused TCG temporary for some DSP opcodes
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmFsqNEACgkQ4+MsLN6t
 wN75Iw//TEBIBmvlJIYHvp01KBHd34211HBsZSGEEssm3cqzjIX6KyAEPnOxQWiy
 +ovvrtL+ha4p6tm4oD1fWRVrQi1DD0rsecIQu7667H2BlPhS3oQJL/jCLExSMcA6
 ZYDp4d+TrlAiRtEki396Ho8dFEOLQYTkhwP5MLE7tY6yZLHPTMLUU1ZDeTbKo9n0
 m60o9UVh72CzsBOM2qwzb4icwxXWPIZguuDqkhS2M5xk2SU8oeg7T11IfvniPrS3
 ykeH9/lA37H7GY/I0Rt2LJssNgWymEBjCoF6AWXGiFiLfsDR/XN4J2xaq85BHdTS
 2JgYFsmTE6Sifx6mTt09WEiLuuXtlExXiOjNP7317MWPdNRR4FuyOlEoNQl2ROo6
 Sy8FCEzi+HM6JMqkCokaboIhnUwWVXMpE4ei5rPhXOx9ZDJAg0mAwqZzp1o3R4KF
 Vbshc7Ey1YGgEFulbdW3crYHmfKkXkRIYUjvsRm2xpZ1tX3H+POkEnGjYFSwzfQ3
 7daZ3/QmR2IBl80z8J/dB7Z/q9CeiZgyJrNHpgeGwvFv0PY0wau1S7NUaUiP48dk
 HEx8riv5VpT331qRC6aCMQ2pcO52sB+jIBPoj+jmEkkjn+o4uRUwXEcbP8jbijS8
 NCfpOyOH9qBF2pYvNAhVzaec9k0HFWN7A8XDqf9UBinBJSR3mZg=
 =MzBZ
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/philmd/tags/mips-20211018' into staging

MIPS patches queue

Hardware emulation:
- Generate FDT blob for Boston machine (Jiaxun)
- VIA chipset cleanups (Zoltan)

TCG:
- Use tcg_constant() in Compact branch and MSA opcodes
- Restrict nanoMIPS DSP MULT[U] opcode accumulator to Rel6
- Fix DEXTRV_S.H DSP opcode
- Remove unused TCG temporary for some DSP opcodes

# gpg: Signature made Sun 17 Oct 2021 03:50:57 PM PDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]

* remotes/philmd/tags/mips-20211018:
  via-ide: Avoid using isa_get_irq()
  vt82c686: Add a method to VIA_ISA to raise ISA interrupts
  vt82c686: Move common code to via_isa_realize
  via-ide: Set user_creatable to false
  target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()
  target/mips: Fix DEXTRV_S.H DSP opcode
  target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()
  target/mips: Use explicit extract32() calls in gen_msa_i5()
  target/mips: Use tcg_constant_i32() in gen_msa_3rf()
  target/mips: Use tcg_constant_i32() in gen_msa_2r()
  target/mips: Use tcg_constant_i32() in gen_msa_2rf()
  target/mips: Use tcg_constant_i32() in gen_msa_elm_df()
  target/mips: Remove unused register from MSA 2R/2RF instruction format
  hw/mips/boston: Add FDT generator
  hw/mips/boston: Allow loading elf kernel and dtb
  hw/mips/boston: Massage memory map information
  target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-10-18 09:16:51 -07:00
parent c148a05721 2792cf20ca
commit 9c050b661d
7 changed files with 415 additions and 110 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
hw/ide/via.c
View File

@ -29,7 +29,7 @@
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "sysemu/dma.h"
#include "hw/isa/vt82c686.h"
#include "hw/ide/pci.h"
#include "trace.h"
@ -112,7 +112,7 @@ static void via_ide_set_irq(void *opaque, int n, int level)
d->config[0x70 + n * 8] &= ~0x80;
}
qemu_set_irq(isa_get_irq(NULL, 14 + n), level);
via_isa_set_irq(pci_get_function_0(d), 14 + n, level);
}
static void via_ide_reset(DeviceState *dev)
@ -217,6 +217,9 @@ static void via_ide_class_init(ObjectClass *klass, void *data)
dc->reset = via_ide_reset;
dc->vmsd = &vmstate_ide_pci;
/* Reason: only works as function of VIA southbridge */
dc->user_creatable = false;
k->realize = via_ide_realize;
k->exit = via_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_VIA;

75
hw/isa/vt82c686.c
View File

@ -542,6 +542,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(ViaISAState, VIA_ISA)
struct ViaISAState {
PCIDevice dev;
qemu_irq cpu_intr;
qemu_irq *isa_irqs;
ISABus *isa_bus;
ViaSuperIOState *via_sio;
};
@ -566,12 +568,42 @@ static const TypeInfo via_isa_info = {
},
};
void via_isa_set_irq(PCIDevice *d, int n, int level)
{
ViaISAState *s = VIA_ISA(d);
qemu_set_irq(s->isa_irqs[n], level);
}
static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
{
ViaISAState *s = opaque;
qemu_set_irq(s->cpu_intr, level);
}
static void via_isa_realize(PCIDevice *d, Error **errp)
{
ViaISAState *s = VIA_ISA(d);
DeviceState *dev = DEVICE(d);
qemu_irq *isa_irq;
int i;
qdev_init_gpio_out(dev, &s->cpu_intr, 1);
isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1);
s->isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d),
&error_fatal);
s->isa_irqs = i8259_init(s->isa_bus, *isa_irq);
isa_bus_irqs(s->isa_bus, s->isa_irqs);
i8254_pit_init(s->isa_bus, 0x40, 0, NULL);
i8257_dma_init(s->isa_bus, 0);
mc146818_rtc_init(s->isa_bus, 2000, NULL);
for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
if (i < PCI_COMMAND || i >= PCI_REVISION_ID) {
d->wmask[i] = 0;
}
}
}
/* TYPE_VT82C686B_ISA */
static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
@ -610,27 +642,10 @@ static void vt82c686b_isa_reset(DeviceState *dev)
static void vt82c686b_realize(PCIDevice *d, Error **errp)
{
ViaISAState *s = VIA_ISA(d);
DeviceState *dev = DEVICE(d);
ISABus *isa_bus;
qemu_irq *isa_irq;
int i;
qdev_init_gpio_out(dev, &s->cpu_intr, 1);
isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1);
isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d),
&error_fatal);
isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq));
i8254_pit_init(isa_bus, 0x40, 0, NULL);
i8257_dma_init(isa_bus, 0);
s->via_sio = VIA_SUPERIO(isa_create_simple(isa_bus,
via_isa_realize(d, errp);
s->via_sio = VIA_SUPERIO(isa_create_simple(s->isa_bus,
TYPE_VT82C686B_SUPERIO));
mc146818_rtc_init(isa_bus, 2000, NULL);
for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
if (i < PCI_COMMAND || i >= PCI_REVISION_ID) {
d->wmask[i] = 0;
}
}
}
static void vt82c686b_class_init(ObjectClass *klass, void *data)
@ -691,26 +706,10 @@ static void vt8231_isa_reset(DeviceState *dev)
static void vt8231_realize(PCIDevice *d, Error **errp)
{
ViaISAState *s = VIA_ISA(d);
DeviceState *dev = DEVICE(d);
ISABus *isa_bus;
qemu_irq *isa_irq;
int i;
qdev_init_gpio_out(dev, &s->cpu_intr, 1);
isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1);
isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d),
&error_fatal);
isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq));
i8254_pit_init(isa_bus, 0x40, 0, NULL);
i8257_dma_init(isa_bus, 0);
s->via_sio = VIA_SUPERIO(isa_create_simple(isa_bus, TYPE_VT8231_SUPERIO));
mc146818_rtc_init(isa_bus, 2000, NULL);
for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
if (i < PCI_COMMAND || i >= PCI_REVISION_ID) {
d->wmask[i] = 0;
}
}
via_isa_realize(d, errp);
s->via_sio = VIA_SUPERIO(isa_create_simple(s->isa_bus,
TYPE_VT8231_SUPERIO));
}
static void vt8231_class_init(ObjectClass *klass, void *data)

371
hw/mips/boston.c
View File

@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "elf.h"
#include "hw/boards.h"
#include "hw/char/serial.h"
#include "hw/ide/pci.h"
@ -48,6 +49,15 @@ typedef struct BostonState BostonState;
DECLARE_INSTANCE_CHECKER(BostonState, BOSTON,
TYPE_BOSTON)
#define FDT_IRQ_TYPE_NONE 0
#define FDT_IRQ_TYPE_LEVEL_HIGH 4
#define FDT_GIC_SHARED 0
#define FDT_GIC_LOCAL 1
#define FDT_BOSTON_CLK_SYS 1
#define FDT_BOSTON_CLK_CPU 2
#define FDT_PCI_IRQ_MAP_PINS 4
#define FDT_PCI_IRQ_MAP_DESCS 6
struct BostonState {
SysBusDevice parent_obj;
@ -64,6 +74,44 @@ struct BostonState {
hwaddr fdt_base;
};
enum {
BOSTON_LOWDDR,
BOSTON_PCIE0,
BOSTON_PCIE1,
BOSTON_PCIE2,
BOSTON_PCIE2_MMIO,
BOSTON_CM,
BOSTON_GIC,
BOSTON_CDMM,
BOSTON_CPC,
BOSTON_PLATREG,
BOSTON_UART,
BOSTON_LCD,
BOSTON_FLASH,
BOSTON_PCIE1_MMIO,
BOSTON_PCIE0_MMIO,
BOSTON_HIGHDDR,
};
static const MemMapEntry boston_memmap[] = {
[BOSTON_LOWDDR] = { 0x0, 0x10000000 },
[BOSTON_PCIE0] = { 0x10000000, 0x2000000 },
[BOSTON_PCIE1] = { 0x12000000, 0x2000000 },
[BOSTON_PCIE2] = { 0x14000000, 0x2000000 },
[BOSTON_PCIE2_MMIO] = { 0x16000000, 0x100000 },
[BOSTON_CM] = { 0x16100000, 0x20000 },
[BOSTON_GIC] = { 0x16120000, 0x20000 },
[BOSTON_CDMM] = { 0x16140000, 0x8000 },
[BOSTON_CPC] = { 0x16200000, 0x8000 },
[BOSTON_PLATREG] = { 0x17ffd000, 0x1000 },
[BOSTON_UART] = { 0x17ffe000, 0x20 },
[BOSTON_LCD] = { 0x17fff000, 0x8 },
[BOSTON_FLASH] = { 0x18000000, 0x8000000 },
[BOSTON_PCIE1_MMIO] = { 0x20000000, 0x20000000 },
[BOSTON_PCIE0_MMIO] = { 0x40000000, 0x40000000 },
[BOSTON_HIGHDDR] = { 0x80000000, 0x0 },
};
enum boston_plat_reg {
PLAT_FPGA_BUILD = 0x00,
PLAT_CORE_CL = 0x04,
@ -275,24 +323,24 @@ type_init(boston_register_types)
static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
{
const uint32_t cm_base = 0x16100000;
const uint32_t gic_base = 0x16120000;
const uint32_t cpc_base = 0x16200000;
uint64_t regaddr;
/* Move CM GCRs */
bl_gen_write_ulong(&p,
cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS),
cm_base);
regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS),
bl_gen_write_ulong(&p, regaddr,
boston_memmap[BOSTON_CM].base);
/* Move & enable GIC GCRs */
bl_gen_write_ulong(&p,
cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS),
gic_base | GCR_GIC_BASE_GICEN_MSK);
regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base
+ GCR_GIC_BASE_OFS),
bl_gen_write_ulong(&p, regaddr,
boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK);
/* Move & enable CPC GCRs */
bl_gen_write_ulong(&p,
cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS),
cpc_base | GCR_CPC_BASE_CPCEN_MSK);
regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base
+ GCR_CPC_BASE_OFS),
bl_gen_write_ulong(&p, regaddr,
boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK);
/*
* Setup argument registers to follow the UHI boot protocol:
@ -333,8 +381,9 @@ static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
ram_low_sz = MIN(256 * MiB, machine->ram_size);
ram_high_sz = machine->ram_size - ram_low_sz;
qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg",
1, 0x00000000, 1, ram_low_sz,
1, 0x90000000, 1, ram_high_sz);
1, boston_memmap[BOSTON_LOWDDR].base, 1, ram_low_sz,
1, boston_memmap[BOSTON_HIGHDDR].base + ram_low_sz,
1, ram_high_sz);
fdt = g_realloc(fdt, fdt_totalsize(fdt));
qemu_fdt_dumpdtb(fdt, fdt_sz);
@ -397,6 +446,222 @@ xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,
return XILINX_PCIE_HOST(dev);
}
static void fdt_create_pcie(void *fdt, int gic_ph, int irq, hwaddr reg_base,
hwaddr reg_size, hwaddr mmio_base, hwaddr mmio_size)
{
int i;
char *name, *intc_name;
uint32_t intc_ph;
uint32_t interrupt_map[FDT_PCI_IRQ_MAP_PINS][FDT_PCI_IRQ_MAP_DESCS];
intc_ph = qemu_fdt_alloc_phandle(fdt);
name = g_strdup_printf("/soc/pci@%" HWADDR_PRIx, reg_base);
qemu_fdt_add_subnode(fdt, name);
qemu_fdt_setprop_string(fdt, name, "compatible",
"xlnx,axi-pcie-host-1.00.a");
qemu_fdt_setprop_string(fdt, name, "device_type", "pci");
qemu_fdt_setprop_cells(fdt, name, "reg", reg_base, reg_size);
qemu_fdt_setprop_cell(fdt, name, "#address-cells", 3);
qemu_fdt_setprop_cell(fdt, name, "#size-cells", 2);
qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", 1);
qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", gic_ph);
qemu_fdt_setprop_cells(fdt, name, "interrupts", FDT_GIC_SHARED, irq,
FDT_IRQ_TYPE_LEVEL_HIGH);
qemu_fdt_setprop_cells(fdt, name, "ranges", 0x02000000, 0, mmio_base,
mmio_base, 0, mmio_size);
qemu_fdt_setprop_cells(fdt, name, "bus-range", 0x00, 0xff);
intc_name = g_strdup_printf("%s/interrupt-controller", name);
qemu_fdt_add_subnode(fdt, intc_name);
qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(fdt, intc_name, "#address-cells", 0);
qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_ph);
qemu_fdt_setprop_cells(fdt, name, "interrupt-map-mask", 0, 0, 0, 7);
for (i = 0; i < FDT_PCI_IRQ_MAP_PINS; i++) {
uint32_t *irqmap = interrupt_map[i];
irqmap[0] = cpu_to_be32(0);
irqmap[1] = cpu_to_be32(0);
irqmap[2] = cpu_to_be32(0);
irqmap[3] = cpu_to_be32(i + 1);
irqmap[4] = cpu_to_be32(intc_ph);
irqmap[5] = cpu_to_be32(i + 1);
}
qemu_fdt_setprop(fdt, name, "interrupt-map",
&interrupt_map, sizeof(interrupt_map));
g_free(intc_name);
g_free(name);
}
static const void *create_fdt(BostonState *s,
const MemMapEntry *memmap, int *dt_size)
{
void *fdt;
int cpu;
MachineState *mc = s->mach;
uint32_t platreg_ph, gic_ph, clk_ph;
char *name, *gic_name, *platreg_name, *stdout_name;
static const char * const syscon_compat[2] = {
"img,boston-platform-regs", "syscon"
};
fdt = create_device_tree(dt_size);
if (!fdt) {
error_report("create_device_tree() failed");
exit(1);
}
platreg_ph = qemu_fdt_alloc_phandle(fdt);
gic_ph = qemu_fdt_alloc_phandle(fdt);
clk_ph = qemu_fdt_alloc_phandle(fdt);
qemu_fdt_setprop_string(fdt, "/", "model", "img,boston");
qemu_fdt_setprop_string(fdt, "/", "compatible", "img,boston");
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1);
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1);
qemu_fdt_add_subnode(fdt, "/cpus");
qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
name = g_strdup_printf("/cpus/cpu@%d", cpu);
qemu_fdt_add_subnode(fdt, name);
qemu_fdt_setprop_string(fdt, name, "compatible", "img,mips");
qemu_fdt_setprop_string(fdt, name, "status", "okay");
qemu_fdt_setprop_cell(fdt, name, "reg", cpu);
qemu_fdt_setprop_string(fdt, name, "device_type", "cpu");
qemu_fdt_setprop_cells(fdt, name, "clocks", clk_ph, FDT_BOSTON_CLK_CPU);
g_free(name);
}
qemu_fdt_add_subnode(fdt, "/soc");
qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1);
qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x1);
fdt_create_pcie(fdt, gic_ph, 2,
memmap[BOSTON_PCIE0].base, memmap[BOSTON_PCIE0].size,
memmap[BOSTON_PCIE0_MMIO].base, memmap[BOSTON_PCIE0_MMIO].size);
fdt_create_pcie(fdt, gic_ph, 1,
memmap[BOSTON_PCIE1].base, memmap[BOSTON_PCIE1].size,
memmap[BOSTON_PCIE1_MMIO].base, memmap[BOSTON_PCIE1_MMIO].size);
fdt_create_pcie(fdt, gic_ph, 0,
memmap[BOSTON_PCIE2].base, memmap[BOSTON_PCIE2].size,
memmap[BOSTON_PCIE2_MMIO].base, memmap[BOSTON_PCIE2_MMIO].size);
/* GIC with it's timer node */
gic_name = g_strdup_printf("/soc/interrupt-controller@%" HWADDR_PRIx,
memmap[BOSTON_GIC].base);
qemu_fdt_add_subnode(fdt, gic_name);
qemu_fdt_setprop_string(fdt, gic_name, "compatible", "mti,gic");
qemu_fdt_setprop_cells(fdt, gic_name, "reg", memmap[BOSTON_GIC].base,
memmap[BOSTON_GIC].size);
qemu_fdt_setprop(fdt, gic_name, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(fdt, gic_name, "#interrupt-cells", 3);
qemu_fdt_setprop_cell(fdt, gic_name, "phandle", gic_ph);
name = g_strdup_printf("%s/timer", gic_name);
qemu_fdt_add_subnode(fdt, name);
qemu_fdt_setprop_string(fdt, name, "compatible", "mti,gic-timer");
qemu_fdt_setprop_cells(fdt, name, "interrupts", FDT_GIC_LOCAL, 1,
FDT_IRQ_TYPE_NONE);
qemu_fdt_setprop_cells(fdt, name, "clocks", clk_ph, FDT_BOSTON_CLK_CPU);
g_free(name);
g_free(gic_name);
/* CDMM node */
name = g_strdup_printf("/soc/cdmm@%" HWADDR_PRIx, memmap[BOSTON_CDMM].base);
qemu_fdt_add_subnode(fdt, name);
qemu_fdt_setprop_string(fdt, name, "compatible", "mti,mips-cdmm");
qemu_fdt_setprop_cells(fdt, name, "reg", memmap[BOSTON_CDMM].base,
memmap[BOSTON_CDMM].size);
g_free(name);
/* CPC node */
name = g_strdup_printf("/soc/cpc@%" HWADDR_PRIx, memmap[BOSTON_CPC].base);
qemu_fdt_add_subnode(fdt, name);
qemu_fdt_setprop_string(fdt, name, "compatible", "mti,mips-cpc");
qemu_fdt_setprop_cells(fdt, name, "reg", memmap[BOSTON_CPC].base,
memmap[BOSTON_CPC].size);
g_free(name);
/* platreg and it's clk node */
platreg_name = g_strdup_printf("/soc/system-controller@%" HWADDR_PRIx,
memmap[BOSTON_PLATREG].base);
qemu_fdt_add_subnode(fdt, platreg_name);
qemu_fdt_setprop_string_array(fdt, platreg_name, "compatible",
(char **)&syscon_compat,
ARRAY_SIZE(syscon_compat));
qemu_fdt_setprop_cells(fdt, platreg_name, "reg",
memmap[BOSTON_PLATREG].base,
memmap[BOSTON_PLATREG].size);
qemu_fdt_setprop_cell(fdt, platreg_name, "phandle", platreg_ph);
name = g_strdup_printf("%s/clock", platreg_name);
qemu_fdt_add_subnode(fdt, name);
qemu_fdt_setprop_string(fdt, name, "compatible", "img,boston-clock");
qemu_fdt_setprop_cell(fdt, name, "#clock-cells", 1);
qemu_fdt_setprop_cell(fdt, name, "phandle", clk_ph);
g_free(name);
g_free(platreg_name);
/* reboot node */
name = g_strdup_printf("/soc/reboot");
qemu_fdt_add_subnode(fdt, name);
qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot");
qemu_fdt_setprop_cell(fdt, name, "regmap", platreg_ph);
qemu_fdt_setprop_cell(fdt, name, "offset", 0x10);
qemu_fdt_setprop_cell(fdt, name, "mask", 0x10);
g_free(name);
/* uart node */
name = g_strdup_printf("/soc/uart@%" HWADDR_PRIx, memmap[BOSTON_UART].base);
qemu_fdt_add_subnode(fdt, name);
qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
qemu_fdt_setprop_cells(fdt, name, "reg", memmap[BOSTON_UART].base,
memmap[BOSTON_UART].size);
qemu_fdt_setprop_cell(fdt, name, "reg-shift", 0x2);
qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", gic_ph);
qemu_fdt_setprop_cells(fdt, name, "interrupts", FDT_GIC_SHARED, 3,
FDT_IRQ_TYPE_LEVEL_HIGH);
qemu_fdt_setprop_cells(fdt, name, "clocks", clk_ph, FDT_BOSTON_CLK_SYS);
qemu_fdt_add_subnode(fdt, "/chosen");
stdout_name = g_strdup_printf("%s:115200", name);
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", stdout_name);
g_free(stdout_name);
g_free(name);
/* lcd node */
name = g_strdup_printf("/soc/lcd@%" HWADDR_PRIx, memmap[BOSTON_LCD].base);
qemu_fdt_add_subnode(fdt, name);
qemu_fdt_setprop_string(fdt, name, "compatible", "img,boston-lcd");
qemu_fdt_setprop_cells(fdt, name, "reg", memmap[BOSTON_LCD].base,
memmap[BOSTON_LCD].size);
g_free(name);
name = g_strdup_printf("/memory@0");
qemu_fdt_add_subnode(fdt, name);
qemu_fdt_setprop_string(fdt, name, "device_type", "memory");
g_free(name);
return fdt;
}
static void boston_mach_init(MachineState *machine)
{
DeviceState *dev;
@ -438,11 +703,15 @@ static void boston_mach_init(MachineState *machine)
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
flash = g_new(MemoryRegion, 1);
memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB,
&error_fatal);
memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);
memory_region_init_rom(flash, NULL, "boston.flash",
boston_memmap[BOSTON_FLASH].size, &error_fatal);
memory_region_add_subregion_overlap(sys_mem,
boston_memmap[BOSTON_FLASH].base,
flash, 0);
memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0);
memory_region_add_subregion_overlap(sys_mem,
boston_memmap[BOSTON_HIGHDDR].base,
machine->ram, 0);
ddr_low_alias = g_new(MemoryRegion, 1);
memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr",
@ -451,32 +720,41 @@ static void boston_mach_init(MachineState *machine)
memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0);
xilinx_pcie_init(sys_mem, 0,
0x10000000, 32 * MiB,
0x40000000, 1 * GiB,
boston_memmap[BOSTON_PCIE0].base,
boston_memmap[BOSTON_PCIE0].size,
boston_memmap[BOSTON_PCIE0_MMIO].base,
boston_memmap[BOSTON_PCIE0_MMIO].size,
get_cps_irq(&s->cps, 2), false);
xilinx_pcie_init(sys_mem, 1,
0x12000000, 32 * MiB,
0x20000000, 512 * MiB,
boston_memmap[BOSTON_PCIE1].base,
boston_memmap[BOSTON_PCIE1].size,
boston_memmap[BOSTON_PCIE1_MMIO].base,
boston_memmap[BOSTON_PCIE1_MMIO].size,
get_cps_irq(&s->cps, 1), false);
pcie2 = xilinx_pcie_init(sys_mem, 2,
0x14000000, 32 * MiB,
0x16000000, 1 * MiB,
boston_memmap[BOSTON_PCIE2].base,
boston_memmap[BOSTON_PCIE2].size,
boston_memmap[BOSTON_PCIE2_MMIO].base,
boston_memmap[BOSTON_PCIE2_MMIO].size,
get_cps_irq(&s->cps, 0), true);
platreg = g_new(MemoryRegion, 1);
memory_region_init_io(platreg, NULL, &boston_platreg_ops, s,
"boston-platregs", 0x1000);
memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0);
"boston-platregs",
boston_memmap[BOSTON_PLATREG].size);
memory_region_add_subregion_overlap(sys_mem,
boston_memmap[BOSTON_PLATREG].base, platreg, 0);
s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2,
s->uart = serial_mm_init(sys_mem, boston_memmap[BOSTON_UART].base, 2,
get_cps_irq(&s->cps, 3), 10000000,
serial_hd(0), DEVICE_NATIVE_ENDIAN);
lcd = g_new(MemoryRegion, 1);
memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8);
memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0);
memory_region_add_subregion_overlap(sys_mem,
boston_memmap[BOSTON_LCD].base, lcd, 0);
chr = qemu_chr_new("lcd", "vc:320x240", NULL);
qemu_chr_fe_init(&s->lcd_display, chr, NULL);
@ -499,10 +777,39 @@ static void boston_mach_init(MachineState *machine)
exit(1);
}
} else if (machine->kernel_filename) {
fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s);
if (fit_err) {
error_report("unable to load FIT image");
exit(1);
uint64_t kernel_entry, kernel_high, kernel_size;
kernel_size = load_elf(machine->kernel_filename, NULL,
cpu_mips_kseg0_to_phys, NULL,
&kernel_entry, NULL, &kernel_high,
NULL, 0, EM_MIPS, 1, 0);
if (kernel_size) {
int dt_size;
g_autofree const void *dtb_file_data, *dtb_load_data;
hwaddr dtb_paddr = QEMU_ALIGN_UP(kernel_high, 64 * KiB);
hwaddr dtb_vaddr = cpu_mips_phys_to_kseg0(NULL, dtb_paddr);
s->kernel_entry = kernel_entry;
if (machine->dtb) {
dtb_file_data = load_device_tree(machine->dtb, &dt_size);
} else {
dtb_file_data = create_fdt(s, boston_memmap, &dt_size);
}
dtb_load_data = boston_fdt_filter(s, dtb_file_data,
NULL, &dtb_vaddr);
/* Calculate real fdt size after filter */
dt_size = fdt_totalsize(dtb_load_data);
rom_add_blob_fixed("dtb", dtb_load_data, dt_size, dtb_paddr);
} else {
/* Try to load file as FIT */
fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s);
if (fit_err) {
error_report("unable to load kernel image");
exit(1);
}
}
gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000,

4
include/hw/isa/vt82c686.h
View File

@ -1,6 +1,8 @@
#ifndef HW_VT82C686_H
#define HW_VT82C686_H
#include "hw/pci/pci.h"
#define TYPE_VT82C686B_ISA "vt82c686b-isa"
#define TYPE_VT82C686B_PM "vt82c686b-pm"
#define TYPE_VT8231_ISA "vt8231-isa"
@ -8,4 +10,6 @@
#define TYPE_VIA_AC97 "via-ac97"
#define TYPE_VIA_MC97 "via-mc97"
void via_isa_set_irq(PCIDevice *d, int n, int level);
#endif

51
target/mips/tcg/msa_translate.c
View File

@ -473,15 +473,12 @@ static void gen_msa_i8(DisasContext *ctx)
static void gen_msa_i5(DisasContext *ctx)
{
#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
uint8_t df = (ctx->opcode >> 21) & 0x3;
int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
uint8_t u5 = (ctx->opcode >> 16) & 0x1f;
uint8_t ws = (ctx->opcode >> 11) & 0x1f;
uint8_t wd = (ctx->opcode >> 6) & 0x1f;
uint8_t u5 = extract32(ctx->opcode, 16, 5);
TCGv_i32 tdf = tcg_const_i32(df);
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
TCGv_i32 tdf = tcg_const_i32(extract32(ctx->opcode, 21, 2));
TCGv_i32 twd = tcg_const_i32(extract32(ctx->opcode, 11, 5));
TCGv_i32 tws = tcg_const_i32(extract32(ctx->opcode, 6, 5));
TCGv_i32 timm = tcg_temp_new_i32();
tcg_gen_movi_i32(timm, u5);
@ -1650,7 +1647,7 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
TCGv_i32 tws = tcg_const_i32(ws);
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tn = tcg_const_i32(n);
TCGv_i32 tdf = tcg_const_i32(df);
TCGv_i32 tdf = tcg_constant_i32(df);
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_SLDI_df:
@ -1748,7 +1745,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
tcg_temp_free_i32(tn);
tcg_temp_free_i32(tdf);
}
static void gen_msa_elm(DisasContext *ctx)
@ -1791,10 +1787,22 @@ static void gen_msa_3rf(DisasContext *ctx)
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
TCGv_i32 twt = tcg_const_i32(wt);
TCGv_i32 tdf = tcg_temp_new_i32();
TCGv_i32 tdf;
/* adjust df value for floating-point instruction */
tcg_gen_movi_i32(tdf, df + 2);
switch (MASK_MSA_3RF(ctx->opcode)) {
case OPC_MUL_Q_df:
case OPC_MADD_Q_df:
case OPC_MSUB_Q_df:
case OPC_MULR_Q_df:
case OPC_MADDR_Q_df:
case OPC_MSUBR_Q_df:
tdf = tcg_constant_i32(df + 1);
break;
default:
tdf = tcg_constant_i32(df + 2);
break;
}
switch (MASK_MSA_3RF(ctx->opcode)) {
case OPC_FCAF_df:
@ -1837,7 +1845,6 @@ static void gen_msa_3rf(DisasContext *ctx)
gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_MUL_Q_df:
tcg_gen_movi_i32(tdf, df + 1);
gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_FCULT_df:
@ -1847,14 +1854,12 @@ static void gen_msa_3rf(DisasContext *ctx)
gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_MADD_Q_df:
tcg_gen_movi_i32(tdf, df + 1);
gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_FCLE_df:
gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_MSUB_Q_df:
tcg_gen_movi_i32(tdf, df + 1);
gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_FCULE_df:
@ -1897,7 +1902,6 @@ static void gen_msa_3rf(DisasContext *ctx)
gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_MULR_Q_df:
tcg_gen_movi_i32(tdf, df + 1);
gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_FSULT_df:
@ -1907,7 +1911,6 @@ static void gen_msa_3rf(DisasContext *ctx)
gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_MADDR_Q_df:
tcg_gen_movi_i32(tdf, df + 1);
gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_FSLE_df:
@ -1917,7 +1920,6 @@ static void gen_msa_3rf(DisasContext *ctx)
gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_MSUBR_Q_df:
tcg_gen_movi_i32(tdf, df + 1);
gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_FSULE_df:
@ -1935,21 +1937,17 @@ static void gen_msa_3rf(DisasContext *ctx)
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
tcg_temp_free_i32(twt);
tcg_temp_free_i32(tdf);
}
static void gen_msa_2r(DisasContext *ctx)
{
#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
(op & (0x7 << 18)))
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
uint8_t ws = (ctx->opcode >> 11) & 0x1f;
uint8_t wd = (ctx->opcode >> 6) & 0x1f;
uint8_t df = (ctx->opcode >> 16) & 0x3;
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
TCGv_i32 twt = tcg_const_i32(wt);
TCGv_i32 tdf = tcg_const_i32(df);
switch (MASK_MSA_2R(ctx->opcode)) {
case OPC_FILL_df:
@ -1960,7 +1958,8 @@ static void gen_msa_2r(DisasContext *ctx)
break;
}
#endif
gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */
gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df),
twd, tws); /* trs */
break;
case OPC_NLOC_df:
switch (df) {
@ -2018,23 +2017,19 @@ static void gen_msa_2r(DisasContext *ctx)
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
tcg_temp_free_i32(twt);
tcg_temp_free_i32(tdf);
}
static void gen_msa_2rf(DisasContext *ctx)
{
#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
(op & (0xf << 17)))
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
uint8_t ws = (ctx->opcode >> 11) & 0x1f;
uint8_t wd = (ctx->opcode >> 6) & 0x1f;
uint8_t df = (ctx->opcode >> 16) & 0x1;
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
TCGv_i32 twt = tcg_const_i32(wt);
/* adjust df value for floating-point instruction */
TCGv_i32 tdf = tcg_const_i32(df + 2);
TCGv_i32 tdf = tcg_constant_i32(df + 2);
switch (MASK_MSA_2RF(ctx->opcode)) {
case OPC_FCLASS_df:
@ -2089,8 +2084,6 @@ static void gen_msa_2rf(DisasContext *ctx)
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
tcg_temp_free_i32(twt);
tcg_temp_free_i32(tdf);
}
static void gen_msa_vec_v(DisasContext *ctx)

6
target/mips/tcg/nanomips_translate.c.inc
View File

@ -1868,6 +1868,9 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_i32 t3 = tcg_temp_new_i32();
if (acc || ctx->insn_flags & ISA_MIPS_R6) {
check_dsp_r2(ctx);
}
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
tcg_gen_trunc_tl_i32(t2, t0);
@ -1925,6 +1928,9 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_i32 t3 = tcg_temp_new_i32();
if (acc || ctx->insn_flags & ISA_MIPS_R6) {
check_dsp_r2(ctx);
}
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
tcg_gen_trunc_tl_i32(t2, t0);

11
target/mips/tcg/translate.c
View File

@ -11857,13 +11857,11 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
} else {
/* OPC_JIC, OPC_JIALC */
TCGv tbase = tcg_temp_new();
TCGv toffset = tcg_temp_new();
TCGv toffset = tcg_constant_tl(offset);
gen_load_gpr(tbase, rt);
tcg_gen_movi_tl(toffset, offset);
gen_op_addr_add(ctx, btarget, tbase, toffset);
tcg_temp_free(tbase);
tcg_temp_free(toffset);
}
break;
default:
@ -13618,7 +13616,6 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
TCGv t0;
TCGv t1;
TCGv v1_t;
TCGv v2_t;
int16_t imm;
if ((ret == 0) && (check_ret == 1)) {
@ -13629,10 +13626,8 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
t0 = tcg_temp_new();
t1 = tcg_temp_new();
v1_t = tcg_temp_new();
v2_t = tcg_temp_new();
gen_load_gpr(v1_t, v1);
gen_load_gpr(v2_t, v2);
switch (op1) {
case OPC_EXTR_W_DSP:
@ -13798,8 +13793,7 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
break;
case OPC_DEXTRV_S_H:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env);
break;
case OPC_DEXTRV_L:
tcg_gen_movi_tl(t0, v2);
@ -13833,7 +13827,6 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(v1_t);
tcg_temp_free(v2_t);
}
/* End MIPSDSP functions. */