target/arm: Use TRANS_FEAT for FMUL_zzx
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220527181907.189259-88-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -3557,25 +3557,13 @@ TRANS_FEAT(FMLS_zzxz, aa64_sve, do_FMLA_zzxz, a, true)
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*** SVE Floating Point Multiply Indexed Group
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*** SVE Floating Point Multiply Indexed Group
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*/
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*/
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static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a)
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static gen_helper_gvec_3_ptr * const fmul_idx_fns[4] = {
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{
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NULL, gen_helper_gvec_fmul_idx_h,
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static gen_helper_gvec_3_ptr * const fns[3] = {
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gen_helper_gvec_fmul_idx_s, gen_helper_gvec_fmul_idx_d,
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gen_helper_gvec_fmul_idx_h,
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};
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gen_helper_gvec_fmul_idx_s,
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TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz,
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gen_helper_gvec_fmul_idx_d,
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fmul_idx_fns[a->esz], a->rd, a->rn, a->rm, a->index,
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};
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a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
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if (sve_access_check(s)) {
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unsigned vsz = vec_full_reg_size(s);
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TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
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tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
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vec_full_reg_offset(s, a->rn),
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vec_full_reg_offset(s, a->rm),
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status, vsz, vsz, a->index, fns[a->esz - 1]);
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tcg_temp_free_ptr(status);
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}
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return true;
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}
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/*
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/*
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*** SVE Floating Point Fast Reduction Group
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*** SVE Floating Point Fast Reduction Group
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