tcg/i386: Use ANDN instruction
Note that the optimizer cannot simplify ANDC X,Y,C to AND X,Y,~C so we must handle constants in the implementation of andc. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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Richard Henderson
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ecc7e84327
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9d2eec202f
@ -91,6 +91,7 @@ static const int tcg_target_call_oarg_regs[] = {
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/* Constants we accept. */
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#define TCG_CT_CONST_S32 0x100
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#define TCG_CT_CONST_U32 0x200
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#define TCG_CT_CONST_I32 0x400
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/* Registers used with L constraint, which are the first argument
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registers on x86_64, and two random call clobbered registers on
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@ -128,6 +129,10 @@ static bool have_movbe;
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# define have_movbe 0
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#endif
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/* We need this symbol in tcg-target.h, and we can't properly conditionalize
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it there. Therefore we always define the variable. */
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bool have_bmi1;
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static uint8_t *tb_ret_addr;
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static void patch_reloc(uint8_t *code_ptr, int type,
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@ -224,6 +229,9 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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case 'Z':
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ct->ct |= TCG_CT_CONST_U32;
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break;
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case 'I':
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ct->ct |= TCG_CT_CONST_I32;
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break;
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default:
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return -1;
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@ -247,6 +255,9 @@ static inline int tcg_target_const_match(tcg_target_long val,
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if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
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return 1;
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}
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if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
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return 1;
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}
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return 0;
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}
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@ -276,6 +287,7 @@ static inline int tcg_target_const_match(tcg_target_long val,
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#define OPC_ARITH_EvIz (0x81)
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#define OPC_ARITH_EvIb (0x83)
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#define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */
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#define OPC_ANDN (0xf2 | P_EXT38)
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#define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3))
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#define OPC_BSWAP (0xc8 | P_EXT)
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#define OPC_CALL_Jz (0xe8)
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@ -1813,6 +1825,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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}
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break;
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OP_32_64(andc):
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if (const_args[2]) {
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tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32,
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args[0], args[1]);
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tgen_arithi(s, ARITH_AND + rexw, args[0], ~args[2], 0);
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} else {
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tcg_out_vex_modrm(s, OPC_ANDN + rexw, args[0], args[2], args[1]);
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}
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break;
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OP_32_64(mul):
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if (const_args[2]) {
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int32_t val;
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@ -2041,6 +2063,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
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{ INDEX_op_and_i32, { "r", "0", "ri" } },
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{ INDEX_op_or_i32, { "r", "0", "ri" } },
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{ INDEX_op_xor_i32, { "r", "0", "ri" } },
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{ INDEX_op_andc_i32, { "r", "r", "ri" } },
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{ INDEX_op_shl_i32, { "r", "0", "ci" } },
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{ INDEX_op_shr_i32, { "r", "0", "ci" } },
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@ -2098,6 +2121,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
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{ INDEX_op_and_i64, { "r", "0", "reZ" } },
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{ INDEX_op_or_i64, { "r", "0", "re" } },
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{ INDEX_op_xor_i64, { "r", "0", "re" } },
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{ INDEX_op_andc_i64, { "r", "r", "rI" } },
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{ INDEX_op_shl_i64, { "r", "0", "ci" } },
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{ INDEX_op_shr_i64, { "r", "0", "ci" } },
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@ -2234,26 +2258,32 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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}
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static void tcg_target_init(TCGContext *s)
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{
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#if !(defined(have_cmov) && defined(have_movbe))
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{
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unsigned a, b, c, d;
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int ret = __get_cpuid(1, &a, &b, &c, &d);
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int max = __get_cpuid_max(0, 0);
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if (max >= 1) {
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__cpuid(1, a, b, c, d);
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#ifndef have_cmov
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/* For 32-bit, 99% certainty that we're running on hardware that
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supports cmov, but we still need to check. In case cmov is not
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available, we'll use a small forward branch. */
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have_cmov = ret && (d & bit_CMOV);
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have_cmov = (d & bit_CMOV) != 0;
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#endif
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#ifndef have_movbe
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/* MOVBE is only available on Intel Atom and Haswell CPUs, so we
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need to probe for it. */
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have_movbe = ret && (c & bit_MOVBE);
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have_movbe = (c & bit_MOVBE) != 0;
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#endif
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}
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if (max >= 7) {
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/* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */
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__cpuid_count(7, 0, a, b, c, d);
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#ifdef bit_BMI
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have_bmi1 = (b & bit_BMI) != 0;
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#endif
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}
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
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@ -73,6 +73,8 @@ typedef enum {
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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#endif
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extern bool have_bmi1;
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/* optional instructions */
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#define TCG_TARGET_HAS_div2_i32 1
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#define TCG_TARGET_HAS_rot_i32 1
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@ -84,7 +86,7 @@ typedef enum {
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_andc_i32 0
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#define TCG_TARGET_HAS_andc_i32 have_bmi1
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#define TCG_TARGET_HAS_orc_i32 0
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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@ -112,7 +114,7 @@ typedef enum {
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_andc_i64 0
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#define TCG_TARGET_HAS_andc_i64 have_bmi1
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#define TCG_TARGET_HAS_orc_i64 0
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#define TCG_TARGET_HAS_eqv_i64 0
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#define TCG_TARGET_HAS_nand_i64 0
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