target/avr: Add instruction translation - Branch Instructions
This includes:
- RJMP, IJMP, EIJMP, JMP
- RCALL, ICALL, EICALL, CALL
- RET, RETI
- CPSE, CP, CPC, CPI
- SBRC, SBRS, SBIC, SBIS
- BRBC, BRBS
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-13-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Michael Rolnik
Philippe Mathieu-Daudé
parent
865f3bb9e1
commit
9d316c75ab
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@ -74,3 +74,36 @@ FMUL 0000 0011 0 ... 1 ... @fmul
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FMULS 0000 0011 1 ... 0 ... @fmul
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FMULSU 0000 0011 1 ... 1 ... @fmul
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DES 1001 0100 imm:4 1011
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#
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# Branch Instructions
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#
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# The 22-bit immediate is partially in the opcode word,
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# and partially in the next. Use append_16 to build the
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# complete 22-bit value.
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%imm_call 4:5 0:1 !function=append_16
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@op_bit .... .... . bit:3 ....
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@op_bit_imm .... .. imm:s7 bit:3
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RJMP 1100 imm:s12
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IJMP 1001 0100 0000 1001
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EIJMP 1001 0100 0001 1001
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JMP 1001 010 ..... 110 . imm=%imm_call
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RCALL 1101 imm:s12
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ICALL 1001 0101 0000 1001
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EICALL 1001 0101 0001 1001
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CALL 1001 010 ..... 111 . imm=%imm_call
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RET 1001 0101 0000 1000
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RETI 1001 0101 0001 1000
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CPSE 0001 00 . ..... .... @op_rd_rr
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CP 0001 01 . ..... .... @op_rd_rr
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CPC 0000 01 . ..... .... @op_rd_rr
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CPI 0011 .... .... .... @op_rd_imm8
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SBRC 1111 110 rr:5 0 bit:3
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SBRS 1111 111 rr:5 0 bit:3
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SBIC 1001 1001 reg:5 bit:3
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SBIS 1001 1011 reg:5 bit:3
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BRBS 1111 00 ....... ... @op_bit_imm
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BRBC 1111 01 ....... ... @op_bit_imm
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@ -144,6 +144,16 @@ static int to_regs_24_30_by_two(DisasContext *ctx, int indx)
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}
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static uint16_t next_word(DisasContext *ctx)
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{
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return cpu_lduw_code(ctx->env, ctx->npc++ * 2);
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}
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static int append_16(DisasContext *ctx, int x)
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{
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return x << 16 | next_word(ctx);
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}
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static bool avr_have_feature(DisasContext *ctx, int feature)
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{
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if (!avr_feature(ctx->env, feature)) {
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@ -960,3 +970,536 @@ static bool trans_DES(DisasContext *ctx, arg_DES *a)
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return true;
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}
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/*
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* Branch Instructions
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*/
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static void gen_jmp_ez(DisasContext *ctx)
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{
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tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);
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tcg_gen_or_tl(cpu_pc, cpu_pc, cpu_eind);
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ctx->bstate = DISAS_LOOKUP;
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}
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static void gen_jmp_z(DisasContext *ctx)
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{
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tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);
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ctx->bstate = DISAS_LOOKUP;
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}
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static void gen_push_ret(DisasContext *ctx, int ret)
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{
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if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
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TCGv t0 = tcg_const_i32((ret & 0x0000ff));
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tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
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tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
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tcg_temp_free_i32(t0);
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} else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
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TCGv t0 = tcg_const_i32((ret & 0x00ffff));
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tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
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tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
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tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
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tcg_temp_free_i32(t0);
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} else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
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TCGv lo = tcg_const_i32((ret & 0x0000ff));
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TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8);
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tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
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tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
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tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
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tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
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tcg_temp_free_i32(lo);
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tcg_temp_free_i32(hi);
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}
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}
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static void gen_pop_ret(DisasContext *ctx, TCGv ret)
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{
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if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
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tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
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tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB);
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} else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
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tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
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tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW);
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tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
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} else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
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TCGv lo = tcg_temp_new_i32();
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TCGv hi = tcg_temp_new_i32();
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tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
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tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
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tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);
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tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
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tcg_gen_deposit_tl(ret, lo, hi, 8, 16);
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tcg_temp_free_i32(lo);
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tcg_temp_free_i32(hi);
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}
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}
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static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
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{
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TranslationBlock *tb = ctx->tb;
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if (ctx->singlestep == 0) {
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tcg_gen_goto_tb(n);
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tcg_gen_movi_i32(cpu_pc, dest);
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tcg_gen_exit_tb(tb, n);
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} else {
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tcg_gen_movi_i32(cpu_pc, dest);
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gen_helper_debug(cpu_env);
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tcg_gen_exit_tb(NULL, 0);
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}
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ctx->bstate = DISAS_NORETURN;
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}
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/*
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* Relative jump to an address within PC - 2K +1 and PC + 2K (words). For
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* AVR microcontrollers with Program memory not exceeding 4K words (8KB) this
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* instruction can address the entire memory from every address location. See
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* also JMP.
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*/
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static bool trans_RJMP(DisasContext *ctx, arg_RJMP *a)
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{
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int dst = ctx->npc + a->imm;
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gen_goto_tb(ctx, 0, dst);
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return true;
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}
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/*
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* Indirect jump to the address pointed to by the Z (16 bits) Pointer
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* Register in the Register File. The Z-pointer Register is 16 bits wide and
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* allows jump within the lowest 64K words (128KB) section of Program memory.
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* This instruction is not available in all devices. Refer to the device
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* specific instruction set summary.
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*/
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static bool trans_IJMP(DisasContext *ctx, arg_IJMP *a)
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{
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if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {
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return true;
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}
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gen_jmp_z(ctx);
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return true;
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}
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/*
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* Indirect jump to the address pointed to by the Z (16 bits) Pointer
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* Register in the Register File and the EIND Register in the I/O space. This
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* instruction allows for indirect jumps to the entire 4M (words) Program
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* memory space. See also IJMP. This instruction is not available in all
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* devices. Refer to the device specific instruction set summary.
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*/
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static bool trans_EIJMP(DisasContext *ctx, arg_EIJMP *a)
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{
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if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {
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return true;
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}
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gen_jmp_ez(ctx);
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return true;
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}
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/*
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* Jump to an address within the entire 4M (words) Program memory. See also
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* RJMP. This instruction is not available in all devices. Refer to the device
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* specific instruction set summary.0
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*/
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static bool trans_JMP(DisasContext *ctx, arg_JMP *a)
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{
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if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) {
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return true;
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}
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gen_goto_tb(ctx, 0, a->imm);
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return true;
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}
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/*
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* Relative call to an address within PC - 2K + 1 and PC + 2K (words). The
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* return address (the instruction after the RCALL) is stored onto the Stack.
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* See also CALL. For AVR microcontrollers with Program memory not exceeding 4K
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* words (8KB) this instruction can address the entire memory from every
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* address location. The Stack Pointer uses a post-decrement scheme during
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* RCALL.
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*/
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static bool trans_RCALL(DisasContext *ctx, arg_RCALL *a)
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{
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int ret = ctx->npc;
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int dst = ctx->npc + a->imm;
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gen_push_ret(ctx, ret);
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gen_goto_tb(ctx, 0, dst);
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return true;
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}
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/*
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* Calls to a subroutine within the entire 4M (words) Program memory. The
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* return address (to the instruction after the CALL) will be stored onto the
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* Stack. See also RCALL. The Stack Pointer uses a post-decrement scheme during
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* CALL. This instruction is not available in all devices. Refer to the device
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* specific instruction set summary.
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*/
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static bool trans_ICALL(DisasContext *ctx, arg_ICALL *a)
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{
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if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {
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return true;
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}
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int ret = ctx->npc;
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gen_push_ret(ctx, ret);
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gen_jmp_z(ctx);
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return true;
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}
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/*
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* Indirect call of a subroutine pointed to by the Z (16 bits) Pointer
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* Register in the Register File and the EIND Register in the I/O space. This
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* instruction allows for indirect calls to the entire 4M (words) Program
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* memory space. See also ICALL. The Stack Pointer uses a post-decrement scheme
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* during EICALL. This instruction is not available in all devices. Refer to
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* the device specific instruction set summary.
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*/
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static bool trans_EICALL(DisasContext *ctx, arg_EICALL *a)
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{
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if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {
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return true;
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}
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int ret = ctx->npc;
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gen_push_ret(ctx, ret);
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gen_jmp_ez(ctx);
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return true;
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}
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/*
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* Calls to a subroutine within the entire Program memory. The return
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* address (to the instruction after the CALL) will be stored onto the Stack.
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* (See also RCALL). The Stack Pointer uses a post-decrement scheme during
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* CALL. This instruction is not available in all devices. Refer to the device
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* specific instruction set summary.
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*/
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static bool trans_CALL(DisasContext *ctx, arg_CALL *a)
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{
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if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) {
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return true;
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}
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int Imm = a->imm;
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int ret = ctx->npc;
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gen_push_ret(ctx, ret);
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gen_goto_tb(ctx, 0, Imm);
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return true;
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}
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/*
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* Returns from subroutine. The return address is loaded from the STACK.
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* The Stack Pointer uses a preincrement scheme during RET.
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*/
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static bool trans_RET(DisasContext *ctx, arg_RET *a)
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{
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gen_pop_ret(ctx, cpu_pc);
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ctx->bstate = DISAS_LOOKUP;
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return true;
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}
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/*
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* Returns from interrupt. The return address is loaded from the STACK and
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* the Global Interrupt Flag is set. Note that the Status Register is not
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* automatically stored when entering an interrupt routine, and it is not
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* restored when returning from an interrupt routine. This must be handled by
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* the application program. The Stack Pointer uses a pre-increment scheme
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* during RETI.
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*/
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static bool trans_RETI(DisasContext *ctx, arg_RETI *a)
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{
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gen_pop_ret(ctx, cpu_pc);
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tcg_gen_movi_tl(cpu_If, 1);
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/* Need to return to main loop to re-evaluate interrupts. */
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ctx->bstate = DISAS_EXIT;
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return true;
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}
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/*
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* This instruction performs a compare between two registers Rd and Rr, and
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* skips the next instruction if Rd = Rr.
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*/
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static bool trans_CPSE(DisasContext *ctx, arg_CPSE *a)
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{
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ctx->skip_cond = TCG_COND_EQ;
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ctx->skip_var0 = cpu_r[a->rd];
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ctx->skip_var1 = cpu_r[a->rr];
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return true;
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}
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/*
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* This instruction performs a compare between two registers Rd and Rr.
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* None of the registers are changed. All conditional branches can be used
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* after this instruction.
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*/
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static bool trans_CP(DisasContext *ctx, arg_CP *a)
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{
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TCGv Rd = cpu_r[a->rd];
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TCGv Rr = cpu_r[a->rr];
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TCGv R = tcg_temp_new_i32();
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tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
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tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
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/* update status register */
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gen_sub_CHf(R, Rd, Rr);
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gen_sub_Vf(R, Rd, Rr);
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gen_ZNSf(R);
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tcg_temp_free_i32(R);
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return true;
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}
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/*
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* This instruction performs a compare between two registers Rd and Rr and
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* also takes into account the previous carry. None of the registers are
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* changed. All conditional branches can be used after this instruction.
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*/
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static bool trans_CPC(DisasContext *ctx, arg_CPC *a)
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{
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TCGv Rd = cpu_r[a->rd];
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TCGv Rr = cpu_r[a->rr];
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TCGv R = tcg_temp_new_i32();
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TCGv zero = tcg_const_i32(0);
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tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
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tcg_gen_sub_tl(R, R, cpu_Cf);
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tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
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/* update status register */
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gen_sub_CHf(R, Rd, Rr);
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gen_sub_Vf(R, Rd, Rr);
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gen_NSf(R);
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/*
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* Previous value remains unchanged when the result is zero;
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* cleared otherwise.
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*/
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tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero);
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tcg_temp_free_i32(zero);
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tcg_temp_free_i32(R);
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return true;
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}
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/*
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* This instruction performs a compare between register Rd and a constant.
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* The register is not changed. All conditional branches can be used after this
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* instruction.
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*/
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static bool trans_CPI(DisasContext *ctx, arg_CPI *a)
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{
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TCGv Rd = cpu_r[a->rd];
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int Imm = a->imm;
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TCGv Rr = tcg_const_i32(Imm);
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TCGv R = tcg_temp_new_i32();
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tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
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tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
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/* update status register */
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gen_sub_CHf(R, Rd, Rr);
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gen_sub_Vf(R, Rd, Rr);
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gen_ZNSf(R);
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tcg_temp_free_i32(R);
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tcg_temp_free_i32(Rr);
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return true;
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}
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/*
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* This instruction tests a single bit in a register and skips the next
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* instruction if the bit is cleared.
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*/
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static bool trans_SBRC(DisasContext *ctx, arg_SBRC *a)
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{
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TCGv Rr = cpu_r[a->rr];
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ctx->skip_cond = TCG_COND_EQ;
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ctx->skip_var0 = tcg_temp_new();
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ctx->free_skip_var0 = true;
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tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit);
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* This instruction tests a single bit in a register and skips the next
|
||||
* instruction if the bit is set.
|
||||
*/
|
||||
static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a)
|
||||
{
|
||||
TCGv Rr = cpu_r[a->rr];
|
||||
|
||||
ctx->skip_cond = TCG_COND_NE;
|
||||
ctx->skip_var0 = tcg_temp_new();
|
||||
ctx->free_skip_var0 = true;
|
||||
|
||||
tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit);
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* This instruction tests a single bit in an I/O Register and skips the
|
||||
* next instruction if the bit is cleared. This instruction operates on the
|
||||
* lower 32 I/O Registers -- addresses 0-31.
|
||||
*/
|
||||
static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
|
||||
{
|
||||
TCGv temp = tcg_const_i32(a->reg);
|
||||
|
||||
gen_helper_inb(temp, cpu_env, temp);
|
||||
tcg_gen_andi_tl(temp, temp, 1 << a->bit);
|
||||
ctx->skip_cond = TCG_COND_EQ;
|
||||
ctx->skip_var0 = temp;
|
||||
ctx->free_skip_var0 = true;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* This instruction tests a single bit in an I/O Register and skips the
|
||||
* next instruction if the bit is set. This instruction operates on the lower
|
||||
* 32 I/O Registers -- addresses 0-31.
|
||||
*/
|
||||
static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a)
|
||||
{
|
||||
TCGv temp = tcg_const_i32(a->reg);
|
||||
|
||||
gen_helper_inb(temp, cpu_env, temp);
|
||||
tcg_gen_andi_tl(temp, temp, 1 << a->bit);
|
||||
ctx->skip_cond = TCG_COND_NE;
|
||||
ctx->skip_var0 = temp;
|
||||
ctx->free_skip_var0 = true;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Conditional relative branch. Tests a single bit in SREG and branches
|
||||
* relatively to PC if the bit is cleared. This instruction branches relatively
|
||||
* to PC in either direction (PC - 63 < = destination <= PC + 64). The
|
||||
* parameter k is the offset from PC and is represented in two's complement
|
||||
* form.
|
||||
*/
|
||||
static bool trans_BRBC(DisasContext *ctx, arg_BRBC *a)
|
||||
{
|
||||
TCGLabel *not_taken = gen_new_label();
|
||||
|
||||
TCGv var;
|
||||
|
||||
switch (a->bit) {
|
||||
case 0x00:
|
||||
var = cpu_Cf;
|
||||
break;
|
||||
case 0x01:
|
||||
var = cpu_Zf;
|
||||
break;
|
||||
case 0x02:
|
||||
var = cpu_Nf;
|
||||
break;
|
||||
case 0x03:
|
||||
var = cpu_Vf;
|
||||
break;
|
||||
case 0x04:
|
||||
var = cpu_Sf;
|
||||
break;
|
||||
case 0x05:
|
||||
var = cpu_Hf;
|
||||
break;
|
||||
case 0x06:
|
||||
var = cpu_Tf;
|
||||
break;
|
||||
case 0x07:
|
||||
var = cpu_If;
|
||||
break;
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
}
|
||||
|
||||
tcg_gen_brcondi_i32(TCG_COND_NE, var, 0, not_taken);
|
||||
gen_goto_tb(ctx, 0, ctx->npc + a->imm);
|
||||
gen_set_label(not_taken);
|
||||
|
||||
ctx->bstate = DISAS_CHAIN;
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Conditional relative branch. Tests a single bit in SREG and branches
|
||||
* relatively to PC if the bit is set. This instruction branches relatively to
|
||||
* PC in either direction (PC - 63 < = destination <= PC + 64). The parameter k
|
||||
* is the offset from PC and is represented in two's complement form.
|
||||
*/
|
||||
static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a)
|
||||
{
|
||||
TCGLabel *not_taken = gen_new_label();
|
||||
|
||||
TCGv var;
|
||||
|
||||
switch (a->bit) {
|
||||
case 0x00:
|
||||
var = cpu_Cf;
|
||||
break;
|
||||
case 0x01:
|
||||
var = cpu_Zf;
|
||||
break;
|
||||
case 0x02:
|
||||
var = cpu_Nf;
|
||||
break;
|
||||
case 0x03:
|
||||
var = cpu_Vf;
|
||||
break;
|
||||
case 0x04:
|
||||
var = cpu_Sf;
|
||||
break;
|
||||
case 0x05:
|
||||
var = cpu_Hf;
|
||||
break;
|
||||
case 0x06:
|
||||
var = cpu_Tf;
|
||||
break;
|
||||
case 0x07:
|
||||
var = cpu_If;
|
||||
break;
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
}
|
||||
|
||||
tcg_gen_brcondi_i32(TCG_COND_EQ, var, 0, not_taken);
|
||||
gen_goto_tb(ctx, 0, ctx->npc + a->imm);
|
||||
gen_set_label(not_taken);
|
||||
|
||||
ctx->bstate = DISAS_CHAIN;
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue