target/riscv: Fix read and write accesses to vsip and vsie
The previous implementation was broken in many ways: - Used mideleg instead of hideleg to mask accesses - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...) Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -749,30 +749,42 @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
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return write_mstatus(env, CSR_MSTATUS, newval);
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}
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static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
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{
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/* Shift the VS bits to their S bit location in vsie */
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*val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
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return 0;
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}
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static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
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{
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if (riscv_cpu_virt_enabled(env)) {
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/* Tell the guest the VS bits, shifted to the S bit locations */
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*val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
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read_vsie(env, CSR_VSIE, val);
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} else {
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*val = env->mie & env->mideleg;
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}
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return 0;
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}
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static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
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{
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/* Shift the S bits to their VS bit location in mie */
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target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
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((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
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return write_mie(env, CSR_MIE, newval);
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}
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static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
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{
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target_ulong newval;
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if (riscv_cpu_virt_enabled(env)) {
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/* Shift the guests S bits to VS */
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newval = (env->mie & ~VS_MODE_INTERRUPTS) |
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((val << 1) & VS_MODE_INTERRUPTS);
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write_vsie(env, CSR_VSIE, val);
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} else {
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newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
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target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
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(val & S_MODE_INTERRUPTS);
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write_mie(env, CSR_MIE, newval);
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}
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return write_mie(env, CSR_MIE, newval);
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return 0;
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}
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static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
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@ -853,17 +865,25 @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
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return 0;
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}
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static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
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target_ulong new_value, target_ulong write_mask)
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{
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/* Shift the S bits to their VS bit location in mip */
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int ret = rmw_mip(env, 0, ret_value, new_value << 1,
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(write_mask << 1) & vsip_writable_mask & env->hideleg);
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*ret_value &= VS_MODE_INTERRUPTS;
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/* Shift the VS bits to their S bit location in vsip */
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*ret_value >>= 1;
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return ret;
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}
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static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
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target_ulong new_value, target_ulong write_mask)
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{
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int ret;
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if (riscv_cpu_virt_enabled(env)) {
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/* Shift the new values to line up with the VS bits */
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ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
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(write_mask & sip_writable_mask) << 1 & env->mideleg);
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ret &= vsip_writable_mask;
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ret >>= 1;
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ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
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} else {
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ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
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write_mask & env->mideleg & sip_writable_mask);
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@ -1122,26 +1142,6 @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
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return 0;
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}
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static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
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target_ulong new_value, target_ulong write_mask)
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{
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int ret = rmw_mip(env, 0, ret_value, new_value,
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write_mask & env->mideleg & vsip_writable_mask);
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return ret;
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}
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static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
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return 0;
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}
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static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
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{
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target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
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return write_mie(env, CSR_MIE, newval);
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}
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static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = env->vstvec;
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