hw/char/pl011: refactor FIFO depth handling code
PL011 can be in either of 2 modes depending guest config: FIFO and single register. The last mode could be viewed as a 1-element-deep FIFO. Current code open-codes a bunch of depth-dependent logic. Refactor FIFO depth handling code to isolate calculating current FIFO depth. One functional (albeit guest-invisible) side-effect of this change is that previously we would always increment s->read_pos in UARTDR read handler even if FIFO was disabled, now we are limiting read_pos to not exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO). Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230123162304.26254-2-eiakovlev@linux.microsoft.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -81,6 +81,17 @@ static void pl011_update(PL011State *s)
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}
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}
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static bool pl011_is_fifo_enabled(PL011State *s)
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{
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return (s->lcr & 0x10) != 0;
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}
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static inline unsigned pl011_get_fifo_depth(PL011State *s)
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{
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/* Note: FIFO depth is expected to be power-of-2 */
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return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
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}
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static uint64_t pl011_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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@ -94,8 +105,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
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c = s->read_fifo[s->read_pos];
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if (s->read_count > 0) {
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s->read_count--;
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if (++s->read_pos == 16)
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s->read_pos = 0;
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s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1);
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}
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if (s->read_count == 0) {
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s->flags |= PL011_FLAG_RXFE;
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@ -273,11 +283,7 @@ static int pl011_can_receive(void *opaque)
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PL011State *s = (PL011State *)opaque;
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int r;
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if (s->lcr & 0x10) {
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r = s->read_count < 16;
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} else {
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r = s->read_count < 1;
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}
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r = s->read_count < pl011_get_fifo_depth(s);
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trace_pl011_can_receive(s->lcr, s->read_count, r);
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return r;
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}
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@ -286,15 +292,15 @@ static void pl011_put_fifo(void *opaque, uint32_t value)
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{
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PL011State *s = (PL011State *)opaque;
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int slot;
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unsigned pipe_depth;
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slot = s->read_pos + s->read_count;
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if (slot >= 16)
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slot -= 16;
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pipe_depth = pl011_get_fifo_depth(s);
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slot = (s->read_pos + s->read_count) & (pipe_depth - 1);
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s->read_fifo[slot] = value;
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s->read_count++;
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s->flags &= ~PL011_FLAG_RXFE;
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trace_pl011_put_fifo(value, s->read_count);
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if (!(s->lcr & 0x10) || s->read_count == 16) {
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if (s->read_count == pipe_depth) {
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trace_pl011_put_fifo_full();
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s->flags |= PL011_FLAG_RXFF;
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}
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@ -359,7 +365,7 @@ static const VMStateDescription vmstate_pl011 = {
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VMSTATE_UINT32(dmacr, PL011State),
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VMSTATE_UINT32(int_enabled, PL011State),
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VMSTATE_UINT32(int_level, PL011State),
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VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16),
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VMSTATE_UINT32_ARRAY(read_fifo, PL011State, PL011_FIFO_DEPTH),
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VMSTATE_UINT32(ilpr, PL011State),
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VMSTATE_UINT32(ibrd, PL011State),
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VMSTATE_UINT32(fbrd, PL011State),
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@ -27,6 +27,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011)
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/* This shares the same struct (and cast macro) as the base pl011 device */
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#define TYPE_PL011_LUMINARY "pl011_luminary"
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/* Depth of UART FIFO in bytes, when FIFO mode is enabled (else depth == 1) */
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#define PL011_FIFO_DEPTH 16
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struct PL011State {
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SysBusDevice parent_obj;
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@ -39,7 +42,7 @@ struct PL011State {
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uint32_t dmacr;
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uint32_t int_enabled;
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uint32_t int_level;
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uint32_t read_fifo[16];
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uint32_t read_fifo[PL011_FIFO_DEPTH];
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uint32_t ilpr;
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uint32_t ibrd;
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uint32_t fbrd;
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