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target/ppc: Remove msr_hv macro 

msr_hv macro hides the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-20-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Víctor Colombo 2022-05-04 18:05:38 -03:00 committed by Daniel Henrique Barboza
parent ca241959cd
commit 9de754d30d
6 changed files with 20 additions and 17 deletions
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11
target/ppc/cpu.h
View File

@ -354,6 +354,12 @@ typedef enum {
#define MSR_RI 1 /* Recoverable interrupt 1 */
#define MSR_LE 0 /* Little-endian mode 1 hflags */
#if defined(TARGET_PPC64)
FIELD(MSR, HV, MSR_HV, 1)
#define FIELD_EX64_HV(storage) FIELD_EX64(storage, MSR, HV)
#else
#define FIELD_EX64_HV(storage) 0
#endif
FIELD(MSR, TS, MSR_TS0, 2)
FIELD(MSR, CM, MSR_CM, 1)
FIELD(MSR, GS, MSR_GS, 1)
@ -489,11 +495,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
#define HFSCR_IC_MSGP 0xA
#if defined(TARGET_PPC64)
#define msr_hv ((env->msr >> MSR_HV) & 1)
#else
#define msr_hv (0)
#endif
#define msr_de ((env->msr >> MSR_DE) & 1)
#define DBCR0_ICMP (1 << 27)

6
target/ppc/cpu_init.c
View File

@ -6305,7 +6305,8 @@ static bool cpu_has_work_POWER9(CPUState *cs)
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
(env->spr[SPR_LPCR] & LPCR_EEE)) {
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
if (!heic || !msr_hv || FIELD_EX64(env->msr, MSR, PR)) {
if (!heic || !FIELD_EX64_HV(env->msr) ||
FIELD_EX64(env->msr, MSR, PR)) {
return true;
}
}
@ -6520,7 +6521,8 @@ static bool cpu_has_work_POWER10(CPUState *cs)
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
(env->spr[SPR_LPCR] & LPCR_EEE)) {
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
if (!heic || !msr_hv || FIELD_EX64(env->msr, MSR, PR)) {
if (!heic || !FIELD_EX64_HV(env->msr) ||
FIELD_EX64(env->msr, MSR, PR)) {
return true;
}
}

8
target/ppc/excp_helper.c
View File

@ -1715,7 +1715,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
/* LPCR will be clear when not supported so this will work */
bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
if ((async_deliver || msr_hv == 0) && hdice) {
if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) {
/* HDEC clears on delivery */
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
powerpc_excp(cpu, POWERPC_EXCP_HDECR);
@ -1727,7 +1727,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
if (env->pending_interrupts & (1 << PPC_INTERRUPT_HVIRT)) {
/* LPCR will be clear when not supported so this will work */
bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE);
if ((async_deliver || msr_hv == 0) && hvice) {
if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) {
powerpc_excp(cpu, POWERPC_EXCP_HVIRT);
return;
}
@ -1738,9 +1738,9 @@ static void ppc_hw_interrupt(CPUPPCState *env)
bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
/* HEIC blocks delivery to the hypervisor */
if ((async_deliver && !(heic && msr_hv &&
if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) &&
!FIELD_EX64(env->msr, MSR, PR))) ||
(env->has_hv_mode && msr_hv == 0 && !lpes0)) {
(env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) {
if (books_vhyp_promotes_external_to_hvirt(cpu)) {
powerpc_excp(cpu, POWERPC_EXCP_HVIRT);
} else {

4
target/ppc/mem_helper.c
View File

@ -612,11 +612,11 @@ void helper_tbegin(CPUPPCState *env)
env->spr[SPR_TEXASR] =
(1ULL << TEXASR_FAILURE_PERSISTENT) |
(1ULL << TEXASR_NESTING_OVERFLOW) |
(msr_hv << TEXASR_PRIVILEGE_HV) |
(FIELD_EX64_HV(env->msr) << TEXASR_PRIVILEGE_HV) |
(FIELD_EX64(env->msr, MSR, PR) << TEXASR_PRIVILEGE_PR) |
(1ULL << TEXASR_FAILURE_SUMMARY) |
(1ULL << TEXASR_TFIAR_EXACT);
env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) |
env->spr[SPR_TFIAR] = env->nip | (FIELD_EX64_HV(env->msr) << 1) |
FIELD_EX64(env->msr, MSR, PR);
env->spr[SPR_TFHAR] = env->nip + 4;
env->crf[0] = 0xB; /* 0b1010 = transaction failure */

2
target/ppc/misc_helper.c
View File

@ -73,7 +73,7 @@ void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
const char *caller, uint32_t cause)
{
#ifdef TARGET_PPC64
if ((env->msr_mask & MSR_HVB) && !msr_hv &&
if ((env->msr_mask & MSR_HVB) && !FIELD_EX64(env->msr, MSR, HV) &&
!(env->spr[SPR_HFSCR] & (1UL << bit))) {
raise_hv_fu_exception(env, bit, caller, cause, GETPC());
}

6
target/ppc/mmu-radix64.c
View File

@ -37,7 +37,7 @@ static bool ppc_radix64_get_fully_qualified_addr(const CPUPPCState *env,
return false;
}
if (msr_hv) { /* MSR[HV] -> Hypervisor/bare metal */
if (FIELD_EX64(env->msr, MSR, HV)) { /* MSR[HV] -> Hypervisor/bare metal */
switch (eaddr & R_EADDR_QUADRANT) {
case R_EADDR_QUADRANT0:
*lpid = 0;
@ -306,7 +306,7 @@ static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate)
if (!(pate->dw0 & PATE0_HR)) {
return false;
}
if (lpid == 0 && !msr_hv) {
if (lpid == 0 && !FIELD_EX64(env->msr, MSR, HV)) {
return false;
}
if ((pate->dw0 & PATE1_R_PRTS) < 5) {
@ -431,7 +431,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
*g_page_size = PRTBE_R_GET_RTS(prtbe0);
base_addr = prtbe0 & PRTBE_R_RPDB;
nls = prtbe0 & PRTBE_R_RPDS;
if (msr_hv || vhyp_flat_addressing(cpu)) {
if (FIELD_EX64(env->msr, MSR, HV) || vhyp_flat_addressing(cpu)) {
/*
* Can treat process table addresses as real addresses
*/