From 9de7b7b5c7ca8e81c6d62b7c5c5a4753fa597bcb Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 12 Apr 2023 13:43:23 +0200 Subject: [PATCH] target/riscv: Move hstatus.spvp check to check_access_hlsv The current cpu_mmu_index value is really irrelevant to the HLV/HSV lookup. Provide the correct priv level directly. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-16-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-16-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 10 +--------- target/riscv/op_helper.c | 2 +- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9dfd1d739b..ccba3c45e7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -770,14 +770,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, use_background = true; } - /* - * MPRV does not affect the virtual-machine load/store - * instructions, HLV, HLVX, and HSV. - */ - if (mmuidx_2stage(mmu_idx)) { - mode = get_field(env->hstatus, HSTATUS_SPVP); - } - if (first_stage == false) { /* * We are in stage 2 translation, this is similar to stage 1. @@ -1250,7 +1242,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, * instructions, HLV, HLVX, and HSV. */ if (mmuidx_2stage(mmu_idx)) { - mode = get_field(env->hstatus, HSTATUS_SPVP); + ; } else if (mode == PRV_M && access_type != MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV)) { mode = get_field(env->mstatus, MSTATUS_MPP); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 6122f5fbe5..f83f7b5347 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } - return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; + return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT; } target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)