target/i386: Create eip_next_*
Create helpers for loading the address of the next insn. Use tcg_constant_* in adjacent code where convenient. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221001140935.465607-16-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -541,6 +541,27 @@ static TCGv_i32 cur_insn_len_i32(DisasContext *s)
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return tcg_constant_i32(cur_insn_len(s));
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}
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static TCGv_i32 eip_next_i32(DisasContext *s)
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{
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/*
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* This function has two users: lcall_real (always 16-bit mode), and
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* iret_protected (16, 32, or 64-bit mode). IRET only uses the value
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* when EFLAGS.NT is set, which is illegal in 64-bit mode, which is
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* why passing a 32-bit value isn't broken. To avoid using this where
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* we shouldn't, return -1 in 64-bit mode so that execution goes into
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* the weeds quickly.
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*/
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if (CODE64(s)) {
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return tcg_constant_i32(-1);
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}
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return tcg_constant_i32(s->pc - s->cs_base);
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}
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static TCGv eip_next_tl(DisasContext *s)
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{
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return tcg_constant_tl(s->pc - s->cs_base);
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}
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/* Compute SEG:REG into A0. SEG is selected from the override segment
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(OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to
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indicate no override. */
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@ -1213,12 +1234,9 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_port, int ot)
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/* user-mode cpu should not be in IOBPT mode */
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g_assert_not_reached();
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#else
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TCGv_i32 t_size = tcg_const_i32(1 << ot);
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TCGv t_next = tcg_const_tl(s->pc - s->cs_base);
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TCGv_i32 t_size = tcg_constant_i32(1 << ot);
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TCGv t_next = eip_next_tl(s);
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gen_helper_bpt_io(cpu_env, t_port, t_size, t_next);
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tcg_temp_free_i32(t_size);
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tcg_temp_free(t_next);
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#endif /* CONFIG_USER_ONLY */
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}
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}
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@ -5324,9 +5342,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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if (dflag == MO_16) {
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tcg_gen_ext16u_tl(s->T0, s->T0);
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}
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next_eip = s->pc - s->cs_base;
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tcg_gen_movi_tl(s->T1, next_eip);
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gen_push_v(s, s->T1);
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gen_push_v(s, eip_next_tl(s));
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gen_op_jmp_v(s->T0);
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gen_bnd_jmp(s);
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s->base.is_jmp = DISAS_JUMP;
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@ -5342,14 +5358,14 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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if (PE(s) && !VM86(s)) {
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tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
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gen_helper_lcall_protected(cpu_env, s->tmp2_i32, s->T1,
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tcg_const_i32(dflag - 1),
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tcg_const_tl(s->pc - s->cs_base));
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tcg_constant_i32(dflag - 1),
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eip_next_tl(s));
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} else {
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tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
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tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
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gen_helper_lcall_real(cpu_env, s->tmp2_i32, s->tmp3_i32,
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tcg_const_i32(dflag - 1),
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tcg_const_i32(s->pc - s->cs_base));
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tcg_constant_i32(dflag - 1),
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eip_next_i32(s));
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}
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s->base.is_jmp = DISAS_JUMP;
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break;
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@ -5372,7 +5388,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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if (PE(s) && !VM86(s)) {
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tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
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gen_helper_ljmp_protected(cpu_env, s->tmp2_i32, s->T1,
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tcg_const_tl(s->pc - s->cs_base));
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eip_next_tl(s));
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} else {
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gen_op_movl_seg_T0_vm(s, R_CS);
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gen_op_jmp_v(s->T1);
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@ -6854,8 +6870,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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}
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gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1));
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} else {
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gen_helper_iret_protected(cpu_env, tcg_const_i32(dflag - 1),
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tcg_const_i32(s->pc - s->cs_base));
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gen_helper_iret_protected(cpu_env, tcg_constant_i32(dflag - 1),
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eip_next_i32(s));
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}
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set_cc_op(s, CC_OP_EFLAGS);
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s->base.is_jmp = DISAS_EOB_ONLY;
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@ -6867,15 +6883,13 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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} else {
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tval = (int16_t)insn_get(env, s, MO_16);
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}
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next_eip = s->pc - s->cs_base;
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tval += next_eip;
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tval += s->pc - s->cs_base;
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if (dflag == MO_16) {
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tval &= 0xffff;
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} else if (!CODE64(s)) {
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tval &= 0xffffffff;
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}
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tcg_gen_movi_tl(s->T0, next_eip);
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gen_push_v(s, s->T0);
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gen_push_v(s, eip_next_tl(s));
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gen_bnd_jmp(s);
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gen_jmp(s, tval);
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}
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@ -7409,8 +7423,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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TCGLabel *l1, *l2, *l3;
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tval = (int8_t)insn_get(env, s, MO_8);
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next_eip = s->pc - s->cs_base;
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tval += next_eip;
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tval += s->pc - s->cs_base;
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if (dflag == MO_16) {
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tval &= 0xffff;
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}
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