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sparc merge (Blue Swirl)

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1620 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2005-11-11 00:24:58 +00:00
parent 4787c71d17
commit 9e61bde56a
6 changed files with 735 additions and 173 deletions
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42
hw/esp.c
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@ -29,6 +29,8 @@
#ifdef DEBUG_ESP #ifdef DEBUG_ESP
#define DPRINTF(fmt, args...) \ #define DPRINTF(fmt, args...) \
do { printf("ESP: " fmt , ##args); } while (0) do { printf("ESP: " fmt , ##args); } while (0)
#define pic_set_irq(irq, level) \
do { printf("ESP: set_irq(%d): %d\n", (irq), (level)); pic_set_irq((irq),(level));} while (0)
#else #else
#define DPRINTF(fmt, args...) #define DPRINTF(fmt, args...)
#endif #endif
@ -38,6 +40,8 @@ do { printf("ESP: " fmt , ##args); } while (0)
#define ESP_MAXREG 0x3f #define ESP_MAXREG 0x3f
#define TI_BUFSZ 65536 #define TI_BUFSZ 65536
#define DMA_VER 0xa0000000 #define DMA_VER 0xa0000000
#define DMA_INTR 1
#define DMA_INTREN 0x10
#define DMA_LOADED 0x04000000 #define DMA_LOADED 0x04000000
typedef struct ESPState { typedef struct ESPState {
@ -66,6 +70,7 @@ typedef struct ESPState {
#define INTR_FC 0x08 #define INTR_FC 0x08
#define INTR_BS 0x10 #define INTR_BS 0x10
#define INTR_DC 0x20 #define INTR_DC 0x20
#define INTR_RST 0x80
#define SEQ_0 0x0 #define SEQ_0 0x0
#define SEQ_CD 0x4 #define SEQ_CD 0x4
@ -98,11 +103,11 @@ static void handle_satn(ESPState *s)
s->ti_rptr = 0; s->ti_rptr = 0;
s->ti_wptr = 0; s->ti_wptr = 0;
if (target > 4 || !s->bd[target]) { // No such drive if (target >= 4 || !s->bd[target]) { // No such drive
s->rregs[4] = STAT_IN; s->rregs[4] = STAT_IN;
s->rregs[5] = INTR_DC; s->rregs[5] = INTR_DC;
s->rregs[6] = SEQ_0; s->rregs[6] = SEQ_0;
s->espdmaregs[0] |= 1; s->espdmaregs[0] |= DMA_INTR;
pic_set_irq(s->irq, 1); pic_set_irq(s->irq, 1);
return; return;
} }
@ -192,7 +197,7 @@ static void handle_satn(ESPState *s)
s->rregs[4] = STAT_IN | STAT_TC | STAT_DI; s->rregs[4] = STAT_IN | STAT_TC | STAT_DI;
s->rregs[5] = INTR_BS | INTR_FC; s->rregs[5] = INTR_BS | INTR_FC;
s->rregs[6] = SEQ_CD; s->rregs[6] = SEQ_CD;
s->espdmaregs[0] |= 1; s->espdmaregs[0] |= DMA_INTR;
pic_set_irq(s->irq, 1); pic_set_irq(s->irq, 1);
} }
@ -209,13 +214,14 @@ static void dma_write(ESPState *s, const uint8_t *buf, uint32_t len)
s->rregs[4] = STAT_IN | STAT_TC | STAT_ST; s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
s->rregs[5] = INTR_BS | INTR_FC; s->rregs[5] = INTR_BS | INTR_FC;
s->rregs[6] = SEQ_CD; s->rregs[6] = SEQ_CD;
s->espdmaregs[0] |= 1;
} else { } else {
memcpy(s->ti_buf, buf, len); memcpy(s->ti_buf, buf, len);
s->ti_size = dmalen; s->ti_size = dmalen;
s->ti_rptr = 0; s->ti_rptr = 0;
s->ti_wptr = 0; s->ti_wptr = 0;
s->rregs[7] = dmalen;
} }
s->espdmaregs[0] |= DMA_INTR;
pic_set_irq(s->irq, 1); pic_set_irq(s->irq, 1);
} }
@ -242,11 +248,12 @@ static void handle_ti(ESPState *s)
s->rregs[4] = STAT_IN | STAT_TC | STAT_ST; s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
s->rregs[5] = INTR_BS; s->rregs[5] = INTR_BS;
s->rregs[6] = 0; s->rregs[6] = 0;
s->espdmaregs[0] |= 1; s->espdmaregs[0] |= DMA_INTR;
} else { } else {
s->ti_size = dmalen; s->ti_size = dmalen;
s->ti_rptr = 0; s->ti_rptr = 0;
s->ti_wptr = 0; s->ti_wptr = 0;
s->rregs[7] = dmalen;
} }
pic_set_irq(s->irq, 1); pic_set_irq(s->irq, 1);
} }
@ -265,6 +272,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
uint32_t saddr; uint32_t saddr;
saddr = (addr & ESP_MAXREG) >> 2; saddr = (addr & ESP_MAXREG) >> 2;
DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
switch (saddr) { switch (saddr) {
case 2: case 2:
// FIFO // FIFO
@ -278,11 +286,16 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
s->ti_wptr = 0; s->ti_wptr = 0;
} }
break; break;
case 5:
// interrupt
// Clear status bits except TC
s->rregs[4] &= STAT_TC;
pic_set_irq(s->irq, 0);
s->espdmaregs[0] &= ~DMA_INTR;
break;
default: default:
break; break;
} }
DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
return s->rregs[saddr]; return s->rregs[saddr];
} }
@ -317,8 +330,9 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
break; break;
case 1: case 1:
DPRINTF("Flush FIFO (%2.2x)\n", val); DPRINTF("Flush FIFO (%2.2x)\n", val);
s->rregs[6] = 0; //s->ti_size = 0;
s->rregs[5] = INTR_FC; s->rregs[5] = INTR_FC;
s->rregs[6] = 0;
break; break;
case 2: case 2:
DPRINTF("Chip reset (%2.2x)\n", val); DPRINTF("Chip reset (%2.2x)\n", val);
@ -326,6 +340,11 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
break; break;
case 3: case 3:
DPRINTF("Bus reset (%2.2x)\n", val); DPRINTF("Bus reset (%2.2x)\n", val);
s->rregs[5] = INTR_RST;
if (!(s->wregs[8] & 0x40)) {
s->espdmaregs[0] |= DMA_INTR;
pic_set_irq(s->irq, 1);
}
break; break;
case 0x10: case 0x10:
handle_ti(s); handle_ti(s);
@ -362,7 +381,10 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
break; break;
case 9 ... 10: case 9 ... 10:
break; break;
case 11 ... 15: case 11:
s->rregs[saddr] = val & 0x15;
break;
case 12 ... 15:
s->rregs[saddr] = val; s->rregs[saddr] = val;
break; break;
default: default:
@ -403,7 +425,7 @@ static void espdma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t va
DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->espdmaregs[saddr], val); DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->espdmaregs[saddr], val);
switch (saddr) { switch (saddr) {
case 0: case 0:
if (!(val & 0x10)) if (!(val & DMA_INTREN))
pic_set_irq(s->irq, 0); pic_set_irq(s->irq, 0);
if (val & 0x80) { if (val & 0x80) {
esp_reset(s); esp_reset(s);

BIN
pc-bios/proll.elf
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Binary file not shown.

840
pc-bios/proll.patch
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File diff suppressed because it is too large Load Diff

8
target-sparc/helper.c
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@ -195,15 +195,17 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu) int is_user, int is_softmmu)
{ {
target_ulong virt_addr;
target_phys_addr_t paddr; target_phys_addr_t paddr;
unsigned long vaddr; unsigned long vaddr;
int error_code = 0, prot, ret = 0, access_index; int error_code = 0, prot, ret = 0, access_index;
error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user); error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
if (error_code == 0) { if (error_code == 0) {
virt_addr = address & TARGET_PAGE_MASK; vaddr = address & TARGET_PAGE_MASK;
vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1)); paddr &= TARGET_PAGE_MASK;
#ifdef DEBUG_MMU
printf("Translate at 0x%lx -> 0x%lx, vaddr 0x%lx\n", (long)address, (long)paddr, (long)vaddr);
#endif
ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu); ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
return ret; return ret;
} }

8
target-sparc/op_helper.c
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@ -276,6 +276,10 @@ void helper_ld_asi(int asi, int size, int sign)
case 4: case 4:
ret = ldl_phys(T0 & ~3); ret = ldl_phys(T0 & ~3);
break; break;
case 8:
ret = ldl_phys(T0 & ~3);
T0 = ldl_phys((T0 + 4) & ~3);
break;
} }
break; break;
default: default:
@ -396,6 +400,10 @@ void helper_st_asi(int asi, int size, int sign)
default: default:
stl_phys(T0 & ~3, T1); stl_phys(T0 & ~3, T1);
break; break;
case 8:
stl_phys(T0 & ~3, T1);
stl_phys((T0 + 4) & ~3, T2);
break;
} }
} }
return; return;

10
target-sparc/translate.c
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@ -1897,6 +1897,11 @@ static void disas_sparc_insn(DisasContext * dc)
#else #else
gen_op_xor_T1_T0(); gen_op_xor_T1_T0();
gen_op_wrpsr(); gen_op_wrpsr();
save_state(dc);
gen_op_next_insn();
gen_op_movl_T0_0();
gen_op_exit_tb();
dc->is_br = 1;
#endif #endif
} }
break; break;
@ -2343,8 +2348,8 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_store_FT0_fpr(rd); gen_op_store_FT0_fpr(rd);
break; break;
case 0x21: /* load fsr */ case 0x21: /* load fsr */
gen_op_ldst(ldf);
gen_op_ldfsr(); gen_op_ldfsr();
gen_op_store_FT0_fpr(rd);
break; break;
case 0x22: /* load quad fpreg */ case 0x22: /* load quad fpreg */
goto nfpu_insn; goto nfpu_insn;
@ -2426,9 +2431,8 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_ldst(stf); gen_op_ldst(stf);
break; break;
case 0x25: /* stfsr, V9 stxfsr */ case 0x25: /* stfsr, V9 stxfsr */
gen_op_load_fpr_FT0(rd);
// XXX
gen_op_stfsr(); gen_op_stfsr();
gen_op_ldst(stf);
break; break;
case 0x26: /* stdfq */ case 0x26: /* stdfq */
goto nfpu_insn; goto nfpu_insn;